PDP Training

Agenda
1. Introduction to PDP
2. Manufacturing & Structure of Panel
3. PDP Driving Characteristics
4. Puccini Training
5. Trouble shooting

1. Introduction to PDP
Concepts of PDP
Power supply
Driving circuit

P/S

UV radiationPhosphor

Visible
emission

Generation
Conversion
Transportation

 Fluorescent Lamp and PDP

Principle of PDP light emission is the same as fluorescent lamp.
2 pieces of glass plates are placed with a small gap of 0.1mm, which is
filled with discharge gas, and one of the glass plate has a transparent
electrode. When 100 and several ten V of voltage is applied to the
electrodes, discharge starts and generates UV light. This UV light
reaches to the other glass plate on which phosphors (R,G,B) are pasted,
and the phosphors convert UV light to visible light.

< Fluorescent lamp >

< PDP >

 History of PDP

3rd Generation
2nd Generation

1st Generation

Size : 30-80 inch

Price : Under $10/inch
Definition : CRT Grade
Efficiency : 2-5 lm/w
FAN Noise : No Fan
Use : Public

Size : 30-60 inch

Price : $10~$20/inch
Definition : CRT Grade
Size : 20-50 inch
Preceding
Efficiency : 1-2 lm/w
Price : $20~$30/inch
FAN Noise
Definition : PJTV
New Production
:
Under
30db
/
No
Fan
Size : 20 inch
Efficiency : 1-1.2 lm/w
Technique
Use
:
High-Income
bracket
Price : $30~$50/inch
FAN Noise : 35-45 db
Business
Use
:
High-Income
Efficiency : 0.5-1 lm/w
bracket / Business Establishing Mass
Use : Business
Production Technique
Upgrading Mass
Upgrading Basic
Production Technique
Technique

1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007

 Merits & Demerits of PDP

< Merits
Merits >
>
<

<
< Demerits
Demerits >
>

ThinType
TypeTV
TV
--Thin
LargeScale
Scale::80
80possible
possible
--Large

--High
HighPower
PowerConsumption
Consumption
--Low
LowBrightness
Brightness

LightWeight
Weight(42
(42Scale)
Scale)
--Light
PDP30kg
30kg//CRT:
CRT:over
over100kg
100kg
::PDP

--High
HighCost
Cost
--Low
LowLighting
LightingEfficiency
Efficiency

LCD40
4032Kg
32Kg
::LCD
WideAngleview
Angleview
--Wide

--Image
ImageRetention
Retention
--Operation
OperationTemperature
Temperature

HighDefinition
Definition
--High
cellpitch
pitch0.1mm
0.1mm
::cell

--Acoustic
AcousticNoise
Noiseof
ofDriving
Driving

Not-Sensitiveto
toMagnetic
MagneticField
Field
--Not-Sensitive
Full-color
--Full-color
GoodNon
Nonlinerity
linerity
--Good
Noneed
needfor
forTFT
TFTlike
likeLCD
LCD
::No

Manufacturing &
Structure of Panel

2. Manufacturing & Structure of Panel

Cell Structure of Panel
Bus electrode

Front panel

Dielectric
MgO layer
Barrier

Address
Electrode

ITO electrode
Phosphors

Back panel

 Cell Structure of Panel

 Electro Arrangement of PDP(SDI Panel - SD)

R1

G1

B1

R2

G2

B2

R3

R852

G852

B852

Y1
X
Y2

Black Stripe

Y480

Refer e nce
- A 1 ,A 2, , , : A ddr es s Electr ode
- Y 1 ,Y 2, , , : Scan & Sus tain Electr ode
- X
: Common & Sus tain Electr ode

 Function of each PDP Cell Components

Transparent
Transparent Electrode
Electrode
-- Forming
Forming Electric
Electric Field
Field
-- Transmitting
Transmitting visible
visible Light
Light

Gas
Gas
-- Discharge
Discharge
-- UV
UV Generation
Generation
Dielectric
Dielectric Layer
Layer
-- Current
Current Limiting
Limiting
-- Transmitting
Transmitting visible
visible Light
Light
-- Storing
Storing wall
wall charge
charge

Bus
Bus Electrode
Electrode
-- Path
Path of
of Discharge
Discharge
Current
Current
-- Preventing
Preventing
Voltage
Voltage Drop
Drop

MgO
MgO Thin
Thin Film
Film
-- 2nd
2nd Electron
Electron Radiation
Radiation
-- Forming
Forming wall
wall charge
charge
Phosphor
Phosphor Layer
Layer
-- Conversion
Conversion of
of
UV
UV
Visible
Visible Light
Light

Address
Address Electrode
Electrode
-- RGB
RGB Data
Data Signal
Signal Input
Input

Driving
Driving Circuit
Circuit
-- Discharge
Discharge Switching
Switching

 Process of Panel Manufacturing

A Front Panel
1

Glass
Invest

2 Transparent
Electrode
3

C Assemble

Assembling
Front/Back Panel

Glass
Invest

Attachment of
Front/Back Panel

Address
Electrode

Dielectric
Layer

Bus
Electrode

3 Exhaust/ Injection
of Gas(Ne,Xe,Ar)

Dielectric
Layer 1

Black
Stripe

Dielectric
Layer 2

MgO
Thin Film

B Back Panel

Aging
Barrier Rib 4

5 Test of Lighting
Phosphor
Layer

Frit Apply

 Process of Panel Manufacturing

D Inter-connection
1

Cleaning
Terminal of
Panel

Attachment
of ACF

E Chassis Assemble
Back Panel
Front

Attachment
of Tape

Attachment
of Heat-proof
sheet

Panel

FPC
ACF
Terminal

Head of Pressing by heat

Attachment
of FPC

Attachment
of Panel

Silicon Apply

Assembling
of Circuits

PDP Driving
Characteristics

3. PDP Driving Characteristics

Function Description by board - 1
.SMPS(Switching Mode Power Supply)
: It is the supplier to provide voltage and current to work the drive voltage and panel in each board.

.X-MAIN BOARD
: It makes the drive wave form by switching FETs to Timing Controlle coming from logic-board and
supplies X electrode of panel with the drive wave form via connector.

.Y-MAIN BOARD
: It makes the drive wave form by switching FETs to Timing Controller coming from the logic-board
and provides Y electrode of panel with the drive wave form via Scan Driver IC on Y buffer board
in order.

.LOGIC MAIN BOARD

: It process image signal and performs buffering of the logic-main board (to create XY drive signal
and output) and the address driver output signal.
Then it supplies the output signal to the address driver IC(COF Module).

 Function Description by board - 2

.LOGIC BUFFER(E,F,G) : It delivers the data signal and control signal to the COF.

.Y-BUFFER (Upper,Lower)
: It is the board to impress the scan waveform on the Y board and consist of 2 boards
(upper board and lower board).
8 Y-buffers are fixed at the scan driver (STV7617 of STC corp. : 64 or 65 Output).

.AC Noise Filter

: It has functions to remove noise(low frequency) coming from AC LINE and prevent surge.
It gives serious effects on the safety regulations (EMC, EMI) according to AC filter.

.COF (Chip on Flexible)

: It impress the Va pulse to the address electrode in the address section and forms the
address discharge by electric potential difference with scanning pulse to be dismissed
by the Y electrode. It is made in the form of COF and one COF consists of 4 Data Drive IC
(STV7610A :96 Output), otherwise single scan is made of 7 COF.

 Effect of Wall Charge

Vw1
Vex+Vw1 >Vf : Discharge
Vex
Y

X
Vw2

X
X

0V

0V

Vex-Vw2 < Vf : No discharge

X

Vex < Vf : No discharge

Different Result with same input pulse Vex according to Wall Charge state

 1 Sub-Field Image Process(ADS Address Data Separate)

Reset

Function
Function
Sustain
SustainErase
Erase
Wall
WallCharge
ChargeSet
Set
Issue
Issue
Operation
Operationmargin
margin
Contrast
Contrast
Short
ShortTime
Time

Address

Sustain

Function
Function
Select
SelectOn
OnCell
Cell

Function
Function
Discharge
DischargeOn
OnCell
Cell

Issue
Issue
High
HighSpeed
Speed
Low
LowVoltage
Voltage
Low
LowFailure
Failure

Issue
Issue
High
HighEfficiency
Efficiency
Low
LowVoltage
Voltage
ERC
ERCPerformance
Performance

 Driving Waveform Specification (P3 Alexander)

Reset

Address

Sustain

Y rising
Ramp

Y sustain
Pulse
Y falling
Ramp

Y scan
Pulse
X sustain
Pulse

A ddres s
Pulse

A1, 2. . . . .
X
Y1, 2. . . .

Addr ess( =Dat a) El ect r ode

Vs

85V

Ve

110V

Common & Sust ai n El ect r ode

Vset

95V

Va

79V

Scan & Sust ai n El ect r ode

Vscan

85V

 Address Operation

In
Inorder
orderto
todisplay
displaypicture,
picture,
select
selectthe
thecells.
cells.

 Sustain Operation

Display
Displaycells
cellsthrough
throughstrong
strong
Sustain
Sustaindischarge.
discharge.

 Combination of R,G,B Light

1 - Pixel
Level of Luminance

RED 4096 Levels

Green 4096 Levels

Blue 4096 Levels

68.7 Billion Colors

 Luminance Control

Number
of Pulses

2048

Lights

2048

 1 Picture Structure by 12 Sub-Field - 1

 1 Picture Structure by 12 Sub-Field - 2

 1 Picture Structure by 12 Sub-Field - 3

 1 Picture Structure by 12 Sub-Field - 4

 1 Picture Structure by 12 Sub-Field - 5

 1 Picture Structure by 12 Sub-Field -

 1 Picture Structure by 12 Sub-Field - 11

 1 Picture Structure by 12 Sub-Field - 12

3. Puccini Training

 Comparison with other Models

Project

Puccini(V4)

Mozart (V3)

Nelson (V3)

Brightness

1300cd/m2

1000cd/m2

1000cd/m2

Contrast ratio

10000:1

3000:1

3000:1

Tuner

1Tuner

2Tuner

1Tuner

Audio out

15W x 2

15W x 2

15W x 2

Sound

SRS Tru Surround XT

SRS Tru Surround XT

SRS Tru Surround XT

Speaker

Included

Included

Not Included

Video input

1Rear

2Rear

1Rear

S-Video input

1Rear

1Rear

1Rear

Component
Input

2Rear

2Rear

1Rear

Side Input

CVBS, S-Video

HDMI

1Rear

Power
Consumption

290W

330W

330W

Etc.

Touch Pad, Melody

Design

 Additional Function of PL42S5S

1. 12bits Signal process and 12bits Panel Drive

2. Energy saving Function

Function
Function

MENU
MENU->
->Picture
Picture->
->Energy
EnergySaving
Saving
**Auto
AutoSaving
Saving(0
(0~~21%
21%Power
Powersaving)
saving)
- -Automatically
adjusts
to
the
surrounding
Automatically adjusts to the surroundingillumination.
illumination.
**Standard
(No
Power
saving)
Standard (No Power saving)
- -Operates
Operatesininstandard
standardmode
moderegardless
regardlessof
of
the
surrounding
illumination.
the surrounding illumination.
**Super
SuperSaving
Saving(21%
(21%Power
Powersaving)
saving)
- -Enters
maximum
power
saving
Enters maximum power savingmode
moderegardless
regardlessof
of
the
surrounding
illumination
the surrounding illumination

 Picture of PL42S5S Set [Back view]

 Picture of Puccini PDP Module [Back view]

 PDP Set Block Diagram

[Whole Block Diagram]
Display

Logic B'd

Data
DRAM

Driver

Y- Main B'd

Row
Driver

Timing
Input
Data

Data
Controller

Processor

Controller

Scan
Timing

Clock :

20MHz

60MHz

40MHz

852 X 480 Pixels

X- Pulse

853 X 3 X 480 Cells

Generator

Generator
Column Driver

Clock :
Clock :
27MHz

PDP Panel

Y- Pulse

Driver
Timing

X- Main B'd

Power B'd

Power Supply

LVDS
main- Board
Deinterlacer

Audio
Processor

Scalar

Video
Decoder

Video
S/W

AD
Converterr

TMDS
Receiverr

Comb
Filter

Image
Enhance
rImage

Micom

Tuner

AC Power
Source
220V

 Wire Diagram
Wire Diagram
DC DC
C N5002
(12P)
C N5006
(13P)
C N5003
(12P)
C N5004
(12P)
C N5007
(13P)
C N5005
(12P)

C N5008
(10P)

SMPS

Y
C N802

C N806
C N101
(30P)

C N5001
(40P)

LA03
CN201

LOGIC

CN401
(50P)

C N402
(50P)

CN806

E- BUFFER
CN1203

C N4001
(9P)
C N4003
(17P)

CN1201

main

F- BUFFER

CN4004
(17P)

CN4005
(17P)
C N4002
(30P)

C N403
(50P)

G- BUFFER

Puccini (PS42S5S)
PS42S5S V ideo Block Diagram

JA 0400

IC400

T MDS

HDMI

Dig ital R,G,B

Sil9993

JA 0401

A nalog R,G ,B

PC
JA 0803

IC500

A nalog Y ,P b,Pr

DDR RA M

Component
JA 0808

A nalog CV BS

A V (V ide o)
JA 0807

IC203
T EA 6425D
Scar t monitor out

A nalog Y /C

A V (S- V ide o)

IC202

JA 100
Scart1(CV B S,Y /C,RGB )
Scar t CV BS ,Y /C

J A 101
Scart2(CV B S,Y /C)

Scar t CV BS ,Y /C

IC502
ST P

main CV BS ,Y /C

IC702
DNIe

Dig ital R,G ,B

Sub CV BS ,Y /C

T EA 6425D

IC300

Scar t R,G,B

SA A 7119

Dig ital 65 6

Dig ital R,G,B

IC200

IC1100

T EA 6425D

DT C34L M85A

Scar t monitor out

IC1101
DT C34L M85A

A ntena
Input

T U1_1

CV BS
IC601
M30620SPGP

JA 0804
Monitor out

SCL 1
SDA 1
SCL 0
SDA 0

Monitor out CV BS
IC608
S3F866B

SCL 0
SDA 0

PS42S5S Sound Block Diagram

JA 0808

A V L /R

A V (S- V ideo/V ide

Monitor out
JA 0805
HDMI

Component L /R

o)
JA 0804

SCL 0/SDA
PC L /R

Out L /R

HDMI L /R IC1000
Out_ L /R
Ex t1 L /R

Out_In1 L /R

T EA 642 Out_In3 L /R
2

HDMI L /R

Out_In1 L /R
Out_In2 L /R

I2S
IC1001

MSP4410
Out_In3 L /R
G

Out L /R

IC1004
NSP6241

Ex t1 L /R
Ex t2 L /R
I2S

JA 0801
PC
JA 0802
Component

JA 100
Scart1
JA 101
Scart2

PC L /R

SCL 1/SDA 1
A V L /R

Component L /R

Out_ L /R

Scart1 L /R IC1002 Out_In2 L /R

T EA 642
Scart2 L /R
2

Scart1 L /R

SCL 1/SDA 1
IC1003
T A S5112

A nalog L /R

Ex t1 L /R
Scart2 L /R
Ex t1 L /R

SCL 1 /SDA 1
CN1000
Connector

 Picture of PL42S5S main Board

 PL42S5S main IC Functional Description

No

Name

Function

STP

main Video Decorder+Deinterlacer+Scaler

DNIe

Image Enhancer

M30620SPGP

SAA7119

sub Video Decorder

SIL9993

HDMI Decorder

S3F8668

sub Micom

MSP4410G

Sound processor

NSP6241

Sound Effect chip

TMQH6- 701A

main Micom

Tuner

 PL42S5S SW update method

1. Connect PC and PDP using RS-232C Cable

RS-232C Cable
2. Double click the Flash download program

3. Click open button

4. Select Download source file(*.mot)

5. Connect Power cord and click Connect, click Program after being activated Program
button

7. Flash Download Completed

6. Now SW upgrade is working

 Calibration (AV/Component/PC mode)

- Factory mode OSD
1.
2.
3.
4.
5.
6.

Calibration
O ption Table
White Balance
SVP- EX
SAA7119
MSP34XX/44XX

T- PCN42PEUS- XXXX
SUB Micom Ver- xx xx

7. YC Delay
8. Adjust
9. DNIe
10. Chip Debugger O FF
11. Checksum
12. Reset
13. Spread Spectrum
14. Logic

1. AV Calibratio n
2. P C Calibratio n
3. DTV Calibratio n
Lattice Pattern for Calibration (MSPG-925 LTH #24 Pattern)

* Calibration mode
1.
2.
3.

AV mode : PAL
Component(DTV) mode : 1280X720@60Hz
PC mode :1024X768@60Hz
You must perform Calibration in the Lattice pattern before adjusting the White Balance
If you perform Calibration in a pattern other than the Lattice pattern, it causes a
malfunction and the operation will not finish
If you perform Calibration press the
in remote control

 White Balance Adjustment

If picture color is wrong, check White Balance condition
Equipment : CA210, Patten : ABL Pattern
Adjust W/B in Factory Mode
Sub brightness and R/G/B Offset controls low light region
Sub contrast and R/G/B Gain controls high light region
Source

AV : PAL composite, Component : 1280*720/60Hz

(PC and HDMI mode is adjusted automatically)
[ Test Pattern : MSPG-945 Series Pattern #16 ]

High Light

Low Light

Toshiba Patten

*Color coordinate
H/L : 265/265 +/- 2
L/L : 275/285 +/- 3

30.0 Ft +/- 2.0Ft

1.2 Ft +/- 0.2Ft

 Picture condition in Factory mode

No
1
2
3
4
5
6
7
8
9

Item
Picture mode
Color Tone mode
Picture Size
Digital NR
DNIe Demo
MCC
Energy Saving
PIP
Color Weakness

Mode
Dynamic
Cool1
Auto Wide
Off
Off
Custom
Standard
Off
Off

Remark
Component/PC/HDMI : Wide

- Factory mode OSD

1. Calibration
2. O ption Table
3. White Balance
4. SVP- EX
5. SAA7119
6. MSP34XX/44XX

7. YC Delay
8. Adjust
9. DNIe
10. Chip Debugger O FF
11. Checksum
12. Reset
13. Spread Spectrum
14. Logic

T- PCN42PEUS- XXXX
SUB Micom Ver- xxxx
- Inside White Balance

No

Item

Range

RF/AV Initial

Component Initial

PC Initial

HDMI Initial

1
2
3
4
5
6
7
8

Sub- Briteness
R- offset
G- offset
B- offset
Sub- Contrast
R- offset
G- offset
B- offset

0~255
0~255
0~255
0~255
0~63
0~255
0~255
0~255

7
138
128
146
36
128
128
148

128
128
128
128
32
128
128
128

130
138
128
144
32
128
128
128

130
138
128
144
32
128
128
128

4. Trouble shooting

 Check List in advance

. Each cable connection condition check
- Cable is connected correctly ?

.Check Voltage
- SMPS Video main Board, SMPS X,Y Drive board, SMPS Logic board

. The chart below shows abnormal condition

 No Power
- Not operate front LED

- Not operate SMPS relay

AC socket i s connect ed
SMPS CN800 ?

Connect AC socket , SMPS CN800

Mai n SMPS Fuse( F801S) i s open?

N
Change Fuse( F801S)

Mai n SMPS CN804- 1

#3 Pi n : STB 5V ?
#5 Pi n PS- ON : 0V ?

N
Change Mai n SMPS

Change mai n Boar d

 SMPS relay on <-> off continually

- Operate Protection circuit because of some Assy problem

Remove Mai n SMPS CN812,

Rel ay ON <- > OFF af t er
Power on ?

Remov e SMPS CN804- 1,

CN803, Shor t CN804- 1
#4Pi n and #5 Pi n Rel ay
ON <- > OFF af t er Powr er
on ?

Change Mai n SMPS

Connect CN812, r emov e DC- DC

SMPS CN2, CN4, CN5 Rel ay
ON <- > OFF af t er Power on ?

Change X Dr i ve

Remov e onl y DC- DC SMPS CN2,

Rel ay ON <- > OFF af t er
Power on ?

Y
Change mai n Boar d

Change DC- DC SMPS

Remov e onl y DC- DC SMPS CN4,

Rel ay ON <- > OFF af t er
Power on ?

Change Y Dr i ve

Remov e onl y DC- DC SMPS

CN810, Rel ay ON <- > OFF
af t er Power on ?

Change Logi c

 No display but sound is normal

- X or Y or Logic or Y Buffer board is abnormal
- main SMPS or DC-DC SMPS output Voltage is abnormal

Remove Mai n SMPS CN812

Vs, Va Vol t age i s nor mal
af t er Power on ?

Change Mai n SMPS

Connect CN809, Remov e

DC- DC SMPS CN2, CN4,
CN4, DC- DC SMPS out put
Vol t age i s nor mal af t er
Power on ?

Change DC- DC SMPS

Y
Di spl ay i s nor mal af t er changi ng Y Dr i ve boar d ?
N
Di spl ay i s nor mal af t er changi ng X Dr i ve boar d ?
N
Di spl ay i s nor mal af t er changi ng Logi c Dr i ve boar d ?
N
Di spl ay i s nor mal af t er changi ng Y Buf f er boar d ?
N

Change PDP Modul e

 No sound but display is normal

- Speaker wire is not connect
- Video main board sound part defect
- Speaker part defect
- Volume level is 0(Non-sense)

Connect speaker wi r e cor r ect l y ?

Connect or change speaker wi r e

mai n Boar d CN0900 I nput

Vol t age i s nor mal ?

Change Vi deo mai n boar d

Change SMPS

 PDP Dot Module SPEC SDI module

I t em
A Zone
Pr oduct

42"
(SD)

Type

(HD)

Remar k

Special Management Items

1) It is Cell-Defect if there are dark, bright,

Dar k

Br i ght

Fl i cker i ng

TOTAL

42"

B Zone

flickering cells over 2 points within

1.5cm in the boundary section.

Dar k

2) Before vibration/dropping test, it should

Br i ght

be decided whether the module is good

Fl i cker i ng

/ badness first.

TOTAL

And after vibration/dropping test,

10

Dar k

Br i ght

Fl i cker i ng

50"

TOTAL

10
3

Br i ght

Fl i cker i ng

63"

10

preceding descriptions on
Specification,
it is Cell-Defect module.

Dar k

TOTAL

if Cell-Defect happens more than

 A-Zone / BZone Size

W
H/4

Zone B

H/2

Zone A

H/4

W/4

W/2
Figure-5. Measuring Area

W/4