DESIGN AND VERIFICATION OF SPI(SERIAL

PERIPHERAL INTERFACE) PROTOCOL

Guide:
Prof.Rajeev Pankaj N.

CHAVAN SUYOG MADHUKAR

13MVD0058

OBJECTIVES
Design Serial Peripheral Interface (SPI ) protocol using Verilog
Verification Using Universal Verification Methodology

Constructing UVM Testbench Architecture using System Verilog

and Object Oriented Programming (OOP).
2. Testcases generation for Functionality Verification
3. Maximize Coverage
4. Finding Bugs
1.

Tool Used QuestaSim (Mentor Graphics)

INTRODUCTION
SPI (Serial Peripheral Interface) is an interface that facilitates the

transfer of synchronous serial data.

SPI (Serial Peripheral Interface) is a synchronous serial data link that
operates in full duplex mode.
It communicates in master/slave mode where the master device
initiates the data frame.
Multiple slave devices are allowed with individual slave select
line(SS).

LITERATURE SURVEY
There are other communication protocols like ETHERNET, USB, PCI-

Express. But these protocols are meant for outside the box
communication.
SPI is often considered for on-board communication or intra-chip

communication.
SPI is well suited for low/medium data transfer speed.

SPI MODULE

SPI CORE ARCHITECTURE

DESIGN FEATURES
Full duplex synchronous serial data transfer
Variable length of transfer word up to 128 bits
MSB or LSB first data transfer
Rx and Tx on both rising or falling edge of serial clock
independently
Fully static synchronous design with one clock domain

OPERATION
OPERATION

WISHBONE INTERFACE SIGNALS

SPI EXTERNAL SIGNALS

CORE REGISTERS LIST

CONTROL AND STATUS REGISTER(CTRL)

VERIFICATION PROCESS
Main purpose is to make sure the device can accomplish the task

successfully
Finding Bugs
Verification avoids product failure by removing the bugs
Integral part of development of any IP core

SYSTEM VERILOG FOR VERIFICATION

Hardware Verification Language
Constrained random stimulus generation
Functional coverage
Higher Level structures ,especially Object Oriented Programming

UNIVERSAL VERIFICATION
METHODOLOGY (UVM)
Open

source library directly provided from Accellera.

Compatible
If

with any HDL simulator that supports SystemVerilog

Testbench is properly designed, it is highly reusable.

Test

cases written as separate classes.

Configurable,
At

Flexible Testbenches

run time, we can decide which testcases to run in which order

TESTBENCH ARCHITECTURE

UVM Class Library

provides all the building blocks : verification components and test

environments.
The library consists of base classes, utilities, and macros.
We can extend this predefined class to create our own class using
Inheritance.
e.g . uvm_monitor,uvm_test,uvm_driver

VERIFICATION PLAN
Description of what features of design need to be exercised and

techniques to be used .
I . Features Extraction Plan
MISO and MOSI signals are properly generated
Data transfer occurs correctly on Negative or positive edge of clock
Transfer of LSB or MSB bit first
Transfer of variable character length word

Verification Plan(Cont.)
II. Coverage Plan
Functional Coverage
Code Coverage
1. Branch Coverage
2. Statement Coverage
3. Toggle Coverage
4. FEC Coverage
. Covergroup is written with all possible coverpoints

TEST CASES OVERVIEW

[1] ASS=1,LSB=1, Tx_NEG=1, Rx_NEG=0, Char length=d4.

[2] ASS=1,LSB=0, Tx_NEG=0, Rx_NEG=1, Char length=d33.
[3] ASS=1,LSB=1, Tx_NEG=1, Rx_NEG=0, Char length=d33.
[4] ASS=1,LSB=0, Tx_NEG=1, Rx_NEG=0, Char length=d65.
[5] ASS=1,LSB=1, Tx_NEG=1, Rx_NEG=0, Char length=d0.
[6] ASS=1,LSB=1, Tx_NEG=1, Rx_NEG=0, Char length=d127.

[1] ASS=1,LSB=1, Tx_NEG=1, Rx_NEG=0, Char length=d4.

UVM REPORT (Transcript Window)

UVM REPORT (Transcript Window)

[2] ASS=1;LSB=0, Tx_NEG=0, Rx_NEG=1, Char length=d33.

23

[3] ASS=1;LSB=0, Tx_NEG=1, Rx_NEG=0, Char length=d33.

24

[4] ASS=1;LSB=1, Tx_NEG=0, Rx_NEG=1, Char length=d65.

25

[5] ASS=1;LSB=0, Tx_NEG=0, Rx_NEG=1, Char length=d0.

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[6] ASS=1;LSB=1, Tx_NEG=1, Rx_NEG=0, Char length=d127.

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FUNCTIONAL COVERAGE REPORT

CODE COVERAGE REPORT

CONCLUSION
The Complete Functionality can be exercised using UVM.
UVM is most efficient way for bug detection.
Developing and Verification of IP becomes very simple by using UVM

REFERENCES
Tianxiang Liu and Yunfeng Wang,IP Design of universal devices SPI Interface, IEEE

conference 2011.
A.K. Oudjida, M.L. Berrandjia, A. Liacha, R. Tiar, K. Tahraoui & Y.N. Alhoumays,
Design and Test of General-Purpose SPI Master/Slave IPs on OPB Bus, 2010 7th
International Multi-Conference on Systems, Signals and Devices.
A.K. Oudjida, M.L. Berrandjia, R. Tiar, A. Liacha, K. Tahraoui, FPGA Implementation of
I2C & SPI Protocols: a Comparative Study.
Frdric Leens, An Introduction to I2C and SPI Protocols, IEEE Instrumentation &
Measurement Magazine. IEEE, February 2009.
Shumit Saha, Md.Ashikur Rahman and Amit Thakur, Design and Implementation of SPI
bus protocol with built in self test capability over FPGA.International Conference on
Electrical Engineering and Information Technology 2014.
Motorola Inc. , SPI Block Guide V03.06.

REFERENCES
Janick Bergeron, Writing Testbenches: Functional Verification of HDL Models, Springer

US, 28-Feb-2003.
Chris Spear, System Verilog for Verification, Springer US
Accellera Organization, Universal Verification Methodology (UVM) 1.1 Class
Reference, June 2011.
Mentor Graphics Verification Academy, Cookbook Online Methodology
Documentation
Mentor Graphics Corporation, Questa SIM Users Manual, 1991-2011.
Verification plan.[online] http://www.testbench.in
Datasheet from Lattice Semiconductor, SPI Wishbone Controller, March 2014.

Thank You!!!