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EEE241
Digital Logic Design
Lecture No. 6
Assistant Professor
1)
Review
How sequential circuits are distinguished from combinational circuits?
2)
What are the two types of sequential circuits? And what is the
distinguishing factor?
3)
2)
4)
5)
6)
7)
8)
Draw symbol
2)
Characteristic table
3)
Characteristic equation
4)
Excitation table
EEE241 DLD
Lecture-06
Outline
Registers
Shift Registers
Ripple Counters
Synchronous Counters
Other Counters
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CIIT-IBD-EE
EEE241 DLD
Lecture-06
Must Reading
Chapter No. 6: Registers and Counters
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CIIT-IBD-EE
EEE241 DLD
Lecture-06
Registers
I0
Group of D Flip-Flops
Synchronized (Single Clock)
Store Data
I1
A0
A1
A2
A3
R
D
R
I2
D
R
I3
CLK
Riaz Hussain (rhussain@comsats.edu.pk)
CIIT-IBD-EE
D
R
Lecture-06
Registers
CLK
I0
I1
I1
I2
A2
A1
A0
Note: New data has to go in
with
clock
Riazevery
Hussain (rhussain@comsats.edu.pk)
11/3/15
A1
A2
A3
I0
A3
A0
I3
I2
R
I3
CLK
Reset EEE241 DLD
CIIT-IBD-EE
D
R
Lecture-06
11/3/15
R
E
G
I
S
T
E
R
LD
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
LD
0
1
CIIT-IBD-EE
Q(t+1)
Q(t)
D
EEE241 DLD
Lecture-06
Loadwe
= 0, block
the flip-flop
inputs are held
0.
When
Should
theCClock
to atkeep
the Data?
There is no positive clock edge, so the flip-flops keep
their current values.
A0
I1
A1
I2
A2
I3
A3
This is called E
clock gating,
Q5 since gates are added to the
D
5
clock signal. G
Q4 similar to those of latches.
Dare
There
I problems
4 timing
Here, Load must
be Q
kept at 1 for the correct length of
S
D
3 no longer.
3 clock cycle) and
time (one
T Q
2
The D
clock
is
delayed
a little
bit by the AND gate.
2
E
Q1 different flip-flops in the
In more
complex
scenarios,
D1
R
Bad Idea
system could receive the clock signal at slightly
D0 times. Q0
different
LD
This clock skew can lead to synchronization
problems.
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I0
Load
CLK
CIIT-IBD-EE
EEE241 DLD
Lecture-06
MUX
HowI0can
we
theQ
Y store D
I1 Svalue for more
current
than one cycle?
I0 MUX
D Q
LetsI1 add aY load input
S
signal LD to the register.
MUX
0
If ILD
= 0,
Y the register
D Q
I
1
S its current
keeps
contents.
I0 MUX
Y
If ILD = 1,
1
S
D Q
the register
stores a new value,
Riaz Hussain
Load(rhussain@comsats.edu.pk)
CLK CIIT-IBD-EE EEE241 DLD
A0
A1
A2
A3
Lecture-06
Shift Registers
A shift register shifts its output once every clock cycle.
4-Bit Shift Register
Serial
Input
SI
SO
Serial
Output
CLK
The circuit and example make it look like the register shifts
right.
But it really depends on your interpretation of the bits. If you
consider Q3 to be the most significant bit instead, then the register
is shifting in the opposite direction!
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EEE241 DLD
Lecture-06
10
A register capable of shifting the binary information held in each cell to its
neighboring cell, in a selected direction
Shift Registers
SI
Q3
Q2
Q1
Q0
SO
CLK
CLK
SI
Q3
Q2
Q1
Q0
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Lecture-06
11
We can add a parallel load, just like we did for regular registers.
When LD = 0, the flip-flop inputs will be SIQ0Q1Q2, so the register shifts on
the next positive clock edge.
When LD = 1, the flip-flop inputs are D0-D3, and a new value is loaded into
the shift register, on the next positive clock edge.
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Registers
13
13 / 28
serial device
computer
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Registers
14
14 / 28
computer
serial device
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Registers
15
15 / 28
GPR's
Size
L1 Cache
L2 Cache
Pentium 4
32 bits
8 KB
512 KB
Athlon XP
32 bits
64 KB
512 KB
Athlon 64
16
64 bits
64 KB
1024 KB
32
64 bits
64 KB
512 KB
Itanium 2
128
64 bits
16 KB
256 KB
MIPS R14000
32
64 bits
32 KB
16 MB
Registers
16
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Registers summary
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Registers
17
17 / 28
Serial Transfer
SI
Clock
Shift
Control
Shift Register A
SO
SI
Shift Register B
CLK
CLK
Clock
Shift
Control
CLK
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Serial Addition
Shift
Control
CLK
SI
Shift Register A
x
S
y FA
C
z
Shift Register B
Initially:
A =Augend; B = Addend
D FF is cleared
Finally:
Transferring the sum,
one bit at a time, into
register A
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CLR
Clear
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19
Parallel-in Parallel-out
Serial-in Serial-out
Serial-in Parallel-out
Parallel-in Serial-out
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CLR
CLK
S1
Q3
Q2
Q1
Q0
S1
Y
S0 MUX
I3 I2 I1 I0
S0
SI
for
SR
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D3
D2
Riaz Hussain (rhussain@comsats.edu.pk)
D1
CIIT-IBD-EE
SI
for
SL
D0
EEE241 DLD
Lecture-06
21
Mode Control
11/3/15
S1
S0
Register
Operation
0
0
1
1
0
1
0
1
No change
Shift right
Shift left
Parallel load
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22
Counters
A register that goes through a prescribed sequence of
states upon the application of input pulses is called a
counter
Two Categories
Ripple
Any flipflop output transition serves as a source for triggering
other flipflops
And not the common clock pulse, i.e. asynchronous sequential
circuit
Synchronous
There is a common clock pulse
23 / 28
Ripple Counters
Binary counter:
T FF
Q3
Q2
T 1
Q1
Q
T 1
Q0
Q
T 1
T 1
CLK
CLR
CLR
CLR
CLR
CLR
CLK
Q0
Q1
Q2
Q3
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Binary counter:
D FF
Q3
Ripple Counters
Q2
Q
Q
Q1
Q0
CLK
CLK
Q0
Q1
Q2
Q3
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1Riaz Hussain
2 (rhussain@comsats.edu.pk)
3
4
8 Lecture-069
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0001
0010
0011
0100
1001
1000
0111
0110
0101
Q3
Q2
Q1
1
K 1
K 1
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Q0
1
K 1
K 1
CIIT-IBD-EE
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Lecture-06
CLK
26
J=0, K=1
FF Resets
Q8: 1->0
27
27 / 28
Decades Counter
Q3 Q2 Q1 Q0
BCD
Counter
BCD
Counter
100s Digit
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Q3 Q2 Q1 Q0
BCD
Counter
10s Digit
Q3 Q2 Q1 Q0
Count
(CLK)
1s Digit
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Q2
Q1
Q0
Enable
To
Next
Stage
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CLK
CIIT-IBD-EE
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Lecture-06
29
Q3
Q2
Q
Q1
Q
Q
Q0
Q
Q
Q
CLK
Up
Up = 1, Down =0:
Up = output
0, Down =1:
Circuit counts up since input comes from Normal
Down
BCD Counter
0
0000
0
1
0001
0
1
0010
0
1
0011
0
1
0100
1
1
1001
0
1000
0111
0110
0101
0
Q3 Q2 Q1 Q0
E
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BCD Counter
0
0000 / 0
0
1
0001 / 0
0
1
0010 / 0
0011 / 0
0
1
0100 / 0
1
1
1001 / 1
0
1000 / 0
0111 / 0
0110 / 0
0101 / 0
0
Q3 Q2 Q1 Q0
y
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CIIT-IBD-EE
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Count
I3
Q3
A3
I2
Q2
A2
I1
Q1
A1
I0
Q0
A0
Count
CLR
1
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CLK
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Unused states
The examples shown so far have all had 2 n states, and used n flip-flops.
But sometimes you may have unused, leftover states.
For example, here is a state table and diagram for a counter that repeatedly
counts from 0 (000) to 5 (101).
What should we put in the table for the two unused states?
To get the simplest possible circuit, fill in dont cares for the next states.
If the circuit somehow ends up in one of the unused states (110 or 111), its
behavior will depend on exactly what the dont cares were filled in with.
Present State
Q2
Q1
Q0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Next State
Q2
Q1
Q0
0
0
0
1
1
0
?
?
0
1
1
0
0
0
?
?
1
0
1
0
1
0
?
?
000
101
001
100
010
011
Present State
Next State
Flip-Flop Inputs
JA KA JB KB JC KC
0 X
0 X 1 X
0 X
1 X X
1 X
X 1 0 X
X 0
0 X 1 X
X 0
1 X X
X 1
X 1 0
JA=KA=B
JB=C, KB=1
JC=B KC=1
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38 /38
28
Ring Counter
A counter with ONLY 1 flip-flop set to 1 at any particular time, all other are cleared.
0001
T3 T2 T1 T0
0010
0100
1000
CLK
T0
2-to-4 Decoder
T1
T2
2-bit counter
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T3
CIIT-IBD-EE
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Lecture-06
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Johnson Counter
A 4 flip-flop ring counter that produces 8 states (not 4).
0000
0001
0011
0111
1000
1100
1110
1111
Q3
Q1
Q2
Q
Q
Q0
Q
Q
CLK
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Homework
Mano
Chapter
6
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6-2
6-3
6-4
6-13
6-14
6-16
6-18
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Lecture-06
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Homework
6-2
6-3
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6-4
Homework
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Homework
6-16 The BCD ripple counter has four flip-flops and 16 states,
of which only 10 are used. Analyze the circuit and
determine the next state for each of the other six unused
states. What will happen if a noise signal sends the circuit
to one of the unused states?
6-18 What operation is performed in the up-down counter
when both the up and down inputs are enabled? Modify
the circuit so that when both inputs are equal to 1, the
counter does not change state, but remains in the same
count.
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