Electrical

Engineering

Islamabad

EEE241
Digital Logic Design

Lecture No. 6

Dr. Riaz Hussain

Assistant Professor

Department of Electrical Engineering

COMSATS Institute of Information Technology, Islamabad

1)

Review
How sequential circuits are distinguished from combinational circuits?

2)

What are the two types of sequential circuits? And what is the
distinguishing factor?

3)

Draw the circuit of an SR latch.

1)

Is it a sequential circuits or a combinational?

2)

Write the Boolean expression for outputs (Q, Q) in terms of inputs.

4)

What are the three basic requirements for a memory element?

5)

Why latches can not be used in real life?

6)

How does FF solve the issues with latches?

7)

What is hold time of a FF?

8)

For JK, T and D FF:

1)

Draw symbol

2)

Characteristic table

3)

Characteristic equation

4)

Excitation table

9)11/3/15What are the

two types
of state diagrams?
Riaz Hussain
(rhussain@comsats.edu.pk)
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Lecture-06

Outline

Registers
Shift Registers
Ripple Counters
Synchronous Counters
Other Counters

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Lecture-06

Must Reading
Chapter No. 6: Registers and Counters

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Lecture-06

Registers
I0
Group of D Flip-Flops
Synchronized (Single Clock)
Store Data
I1

A0

A1

A2

A3

R
D
R

I2

D
R

I3
CLK
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Reset EEE241 DLD

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D
R

Lecture-06

Registers
CLK

I0

I1

I1
I2

A2
A1
A0
Note: New data has to go in
with
clock
Riazevery
Hussain (rhussain@comsats.edu.pk)
11/3/15

A1

A2

A3

I0
A3

A0

I3
I2

R
I3
CLK
Reset EEE241 DLD

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D
R

Lecture-06

Registers with Parallel Load

Control Loading the Register with New Data
D7
D6
D5
D4
D3
D2
D1
D0

11/3/15

R
E
G
I
S
T
E
R
LD

Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0

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LD
0
1

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Q(t+1)
Q(t)
D

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Lecture-06

Registers with Parallel Load

We could implement the load ability by playing games with

the CLK input, as shown below.

Loadwe
= 0, block
the flip-flop
inputs are held
0.
When
Should
theCClock
to atkeep
the Data?
There is no positive clock edge, so the flip-flops keep
their current values.

When Load = 1, the CLK input passes through the

Q7 can receive a positive clock
7
ANDD
gate,
so the flip-flops
edgeD
and can R
load a Q
new value from the D3-D0 inputs.
6

A0

I1

A1

I2

A2

I3

A3

This is called E
clock gating,
Q5 since gates are added to the
D
5
clock signal. G
Q4 similar to those of latches.
Dare
There
I problems
4 timing
Here, Load must
be Q
kept at 1 for the correct length of
S
D
3 no longer.
3 clock cycle) and
time (one
T Q
2
The D
clock
is
delayed
a little
bit by the AND gate.
2
E
Q1 different flip-flops in the
In more
complex
scenarios,
D1
R
Bad Idea
system could receive the clock signal at slightly
D0 times. Q0
different
LD
This clock skew can lead to synchronization
problems.

11/3/15

I0

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Load
CLK

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Registers with Parallel Load

The
Circulate the
oldinput
data D3-D0 is copied to
the output Q3-Q0 on every
clock cycle.
I0
I1
I2
I3
11/3/15

MUX
HowI0can
we
theQ
Y store D
I1 Svalue for more
current
than one cycle?
I0 MUX
D Q
LetsI1 add aY load input
S
signal LD to the register.
MUX
0
If ILD
= 0,
Y the register
D Q
I
1
S its current
keeps
contents.
I0 MUX
Y
If ILD = 1,
1
S

D Q
the register
stores a new value,
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A0
A1
A2
A3
Lecture-06

Shift Registers
A shift register shifts its output once every clock cycle.
4-Bit Shift Register

Serial
Input

SI

SO
Serial
Output

CLK

The circuit and example make it look like the register shifts
right.
But it really depends on your interpretation of the bits. If you
consider Q3 to be the most significant bit instead, then the register
is shifting in the opposite direction!
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A register capable of shifting the binary information held in each cell to its
neighboring cell, in a selected direction

Shift Registers
SI

Q3

Q2

Q1

Q0

SO

CLK
CLK
SI
Q3
Q2
Q1
Q0

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Shift registers with parallel load

We can add a parallel load, just like we did for regular registers.
When LD = 0, the flip-flop inputs will be SIQ0Q1Q2, so the register shifts on
the next positive clock edge.
When LD = 1, the flip-flop inputs are D0-D3, and a new value is loaded into
the shift register, on the next positive clock edge.

Serial data transfer

One application of shift registers is converting between serial data and

parallel data.
Computers typically work with multiple-bit quantities.
ASCII text characters are 8 bits long.
Integers, single-precision floating-point numbers, and screen pixels are up
to 32 bits long.
But sometimes its necessary to send or receive data serially, or one bit at a
time. Some examples include:
Input devices such as keyboards and mice.
Output devices like printers.
Any serial port, USB or Firewire device transfers data serially.
Recent switch from Parallel ATA to Serial ATA in hard drives.

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Registers

13

13 / 28

Receiving serial data

To receive serial data using a shift register:

The serial device is connected to the registers SI input.
The shift register outputs Q3-Q0 are connected to the computer.
The serial device transmits one bit of data per clock cycle.
These bits go into the SI input of the shift register.
After four clock cycles, the shift register will hold a four-bit word.
The computer then reads all four bits at once from the Q3-Q0 outputs.

serial device

computer
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Registers

14

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Sending data serially

To send data serially with a shift register, you do the opposite:

The CPU is connected to the registers D inputs.
The shift output (Q3 in this case) is connected to the serial device.
The computer first stores a four-bit word in the register, in one cycle.
The serial device can then read the shift output.
One bit appears on Q3 on each clock cycle.
After four cycles, the entire four-bit word will have been sent.

computer

serial device

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Registers

15

15 / 28

Registers in Modern Hardware

Registers store data in the CPU
Used to supply values to the ALU.
Used to store the results.
If we can use registers, why bother with RAM?
CPU

GPR's

Size

L1 Cache

L2 Cache

Pentium 4

32 bits

8 KB

512 KB

Athlon XP

32 bits

64 KB

512 KB

Athlon 64

16

64 bits

64 KB

1024 KB

Pow erPC 970 (G5)

32

64 bits

64 KB

512 KB

Itanium 2

128

64 bits

16 KB

256 KB

MIPS R14000

32

64 bits

32 KB

16 MB

Answer: Registers are expensive!

Registers occupy the most expensive space
on a chip the core.
L1 and L2 are very fast RAM but not as
fast as registers.
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Registers

16

16 / 28

Registers summary

A register is a special state machine that stores multiple bits of data.

Several variations are possible:
Parallel loading to store data into the register.
Shifting the register contents either left or right.
Counters are considered a type of register too!
One application of shift registers is converting between serial and
parallel data.
Most programs need more storage space than registers provide.
Well introduce RAM to address this problem.
Registers are a central part of modern processors, as we will see in
coming weeks.

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Registers

17

17 / 28

To prevent the loss of information stored in the source register, the

The serial transfer of information from register A to register B is done with
information in register A is made to circulate by connecting the serial output
shift registers
to its serial input

Serial Transfer

SI
Clock
Shift
Control

Shift Register A

SO

SI

Shift Register B
CLK

CLK

Clock
Shift
Control
CLK

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18

Operations in digital computers are usually done in parallel

because that is a faster mode of operation. Serial operations are
slower because a datapath operation takes several clock cycles,
but serial operations have the advantage of requiring fewer
hardware components.

Serial Addition

Shift
Control

CLK

SI
Shift Register A

x
S
y FA
C
z

Shift Register B
Initially:
A =Augend; B = Addend
D FF is cleared
Finally:
Transferring the sum,
one bit at a time, into
register A

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CLR
Clear

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Universal Shift Register

Unidirectional, Bidirectional and Universal
Universal Shift Register:
SR, SL and Parallel Load capability

Parallel-in Parallel-out
Serial-in Serial-out
Serial-in Parallel-out
Parallel-in Serial-out

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Universal Shift Register

CLR
CLK
S1

Q3

Q2

Q1

Q0

S1

Y
S0 MUX
I3 I2 I1 I0

S0
SI
for
SR
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D3

D2
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D1
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SI
for
SL

D0
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21

Universal Shift Register

Q3 Q2 Q1 Q0 CLR
S1
S0
USR
SRin D3 D2 D1 D0 SLin

Mode Control

11/3/15

S1

S0

Register
Operation

0
0
1
1

0
1
0
1

No change
Shift right
Shift left
Parallel load

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22

Counters
A register that goes through a prescribed sequence of
states upon the application of input pulses is called a
counter
Two Categories
Ripple
Any flipflop output transition serves as a source for triggering
other flipflops
And not the common clock pulse, i.e. asynchronous sequential
circuit

Synchronous
There is a common clock pulse
23 / 28

Ripple Counters
Binary counter:
T FF
Q3

Q2
T 1

Q1
Q

T 1

Q0
Q

T 1

T 1
CLK

CLR

CLR

CLR

CLR

CLR
CLK
Q0
Q1
Q2
Q3

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 Binary counter:
D FF

Q3

Ripple Counters
Q2

Q
Q

Q1

Q0

CLK

CLK
Q0
Q1
Q2
Q3
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4

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25

BCD Ripple Counter

0000

0001

0010

0011

0100

1001

1000

0111

0110

0101

Q3

Q2

Q1
1

K 1

K 1

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Q0
1

K 1

K 1

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CLK

26

Logic Diagram of BCD Ripple Counter

Verification: Does the circuit follow the states?
Q1 is complemented with every count (J=K=1)
Q2 complements if Q1 goes from 1 to 0 and Q8 is 0
Q2 remains 0 if Q8 becomes 1
Q4 complements if Q2 goes from 1 to 0
Q8 remains 0 as long as Q2 or Q4 is 0
When Q2 and Q4 are 1, Q8 complements when Q1
goes from 1 to 0. Q8 clears and the next Q1 transition.

J=0, K=1
FF Resets
Q8: 1->0

27
27 / 28

Decades Counter
Q3 Q2 Q1 Q0

BCD
Counter

BCD
Counter

100s Digit

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Q3 Q2 Q1 Q0

BCD
Counter

10s Digit

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Q3 Q2 Q1 Q0

Count
(CLK)

1s Digit

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Synchronous Binary Counter

A flip-flop is complemented if all lower bits are 1.
Q3

Q2

Q1

Q0
Enable

To
Next
Stage
11/3/15

CLK

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29

Up-Down Binary Counter

In a down binary counter

Change an up counter to a down counter:

a) The least significant bit is always complemented

The AND gates should come from the

b) a bit is complemented if all lower bits are 0.

complement outputs instead of the normal one

Q3

Q2
Q

Q1
Q
Q

Q0
Q
Q

Q
CLK

Up
Up = 1, Down =0:
Up = output
0, Down =1:
Circuit counts up since input comes from Normal

Down

Circuit counts down since input comes from Complemented output

BCD Counter
0
0000

0
1

0001

0
1

0010

0
1

0011

0
1

0100
1

1
1001
0

1000

0111

0110

0101
0

Q3 Q2 Q1 Q0
E

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BCD Counter
0
0000 / 0

0
1

0001 / 0

0
1

0010 / 0

0011 / 0

0
1

0100 / 0
1

1
1001 / 1
0

1000 / 0

0111 / 0

0110 / 0

0101 / 0
0

Q3 Q2 Q1 Q0
y

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32

Binary Counter with Parallel Load

Sometimes we need an initial value prior to the count operation.
Initial value: I3 I2 I1 I0
I3
Q3
CLR LD Count Q(t+1)
I2
Q2
0
x
x
0
I1
Q1
1
0
0
Q(t)
I0
Q0
1
0
1
Q(t)+1
LD
1
1
x
I
Count
CLR
Usually Asynchronous Clear
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BCD Counter Example

LD

Count

I3

Q3

A3

I2

Q2

A2

I1

Q1

A1

I0

Q0

A0

Count
CLR
1

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CLK
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BCD counter with parallel load

In part a, 1001 is detected. In part b, 1010 is detected.
In part a, LOAD is set to 1 and effective next cycle. In part b, counter is immediately cleared

35 / 28

Unused states

The examples shown so far have all had 2 n states, and used n flip-flops.
But sometimes you may have unused, leftover states.
For example, here is a state table and diagram for a counter that repeatedly
counts from 0 (000) to 5 (101).
What should we put in the table for the two unused states?
To get the simplest possible circuit, fill in dont cares for the next states.
If the circuit somehow ends up in one of the unused states (110 or 111), its
behavior will depend on exactly what the dont cares were filled in with.
Present State
Q2
Q1
Q0
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Next State
Q2
Q1
Q0
0
0
0
1
1
0
?
?

0
1
1
0
0
0
?
?

1
0
1
0
1
0
?
?

000
101

001

100

010
011

Other Counters: Counters with unused states

Present State

Next State

Flip-Flop Inputs

JA KA JB KB JC KC

0 X

0 X 1 X

0 X

1 X X

1 X

X 1 0 X

X 0

0 X 1 X

X 0

1 X X

X 1

X 1 0

JA=KA=B
JB=C, KB=1
JC=B KC=1

37 / 28

Other Counters: Counters with unused states

What happens if we fall in unused states?

In this case, 111 results in 000. 011 results in
100.
The Counter is self-correcting.

38 /38
28

Ring Counter
A counter with ONLY 1 flip-flop set to 1 at any particular time, all other are cleared.

0001

T3 T2 T1 T0

0010

0100

1000

CLK
T0

2-to-4 Decoder

T1
T2

2-bit counter

11/3/15

T3

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Johnson Counter
A 4 flip-flop ring counter that produces 8 states (not 4).
0000

0001

0011

0111

1000

1100

1110

1111

Q3

Q1

Q2
Q
Q

Q0
Q

Q
CLK

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Homework

Mano
Chapter
6

11/3/15

6-2
6-3
6-4
6-13
6-14
6-16
6-18

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Homework

6-2

Include a synchronous clear input to the Register with

Parallel Load. The modified register will have a parallel
load capability and a synchronous clear capability. The
register is cleared synchronously when the clock goes
through a positive transition and the clear input is equal
to 1.

6-3

What is the difference between serial and parallel

transfer? Explain how to convert serial data to parallel
and parallel data to serial. What type of register is
needed?

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6-4

Homework

The content of a 4-bit register is initially 1101. The

register is shifted six times to the right with the serial
input being 101101. What is the content of the register
after each shift?

6-13 Show that a BCD ripple counter can be constructed using

a 4-bit binary ripple counter with asynchronous clear and
a NAND gate that detects the occurrence of count 1010.
6-14 How many flip-flop will be complemented in a 10-bit
binary ripple counter to reach the next count after the
following count:
(a) 1001100111
(b) 0011111111
(c) 1111111111
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Homework

6-16 The BCD ripple counter has four flip-flops and 16 states,
of which only 10 are used. Analyze the circuit and
determine the next state for each of the other six unused
states. What will happen if a noise signal sends the circuit
to one of the unused states?
6-18 What operation is performed in the up-down counter
when both the up and down inputs are enabled? Modify
the circuit so that when both inputs are equal to 1, the
counter does not change state, but remains in the same
count.

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