Escolar Documentos
Profissional Documentos
Cultura Documentos
using HDL
PREPARED BY
ANKUR RATHI
ASST PROF.
EC DEPARTMENT
Behavioral Modelling
Behavioral Modeling
Structured Procedures
Initial Block
Executes exactly once during simulation
Starts at simulation time 0
reg x, y, z;
initial
begin
// complex statement
x = 1`b0; y = 1`b1; z = 1`b0;
#10 x = 1`b1; y = 1`b1; z = 1`b1;
end
initial
x = 1`b0; // single statement
Always Block
Starts at simulation time 0
Executes continuously during simulation
reg clock;
initial clock = 1`b0;
always #5 clock = ~clock;
Procedural Assignments
Two types
1. Blocking
2. Non-blocking
Blocking Assignment
Executed in the specified order
Use the = operator
// blocking assignments
initial
begin
x = #5 1'b0 ; // at time 5
y = #3 1'b1 ; // at time 8
z = #6 1'b0 ; // at time 14
end
Race Condition
// using blocking assignment statements
always @(posedge clock) // has race condition
x = y;
always @(posedge clock)
y = x;
Timing Control
Delay timing control
@(posedge clock)
@( negedge clock)
A named event
Event received_data ;
// declare
always @(posedge clock)
if (last_byte)
-> received_data ;
// trigger
always @(received_data) // recognize
begin
... end
Event or Control
Event or control
or,
* or (*) means any signals
Selection Statements
if...else statement
case (casex/casez) statement
if...else Statement
Syntax
if (<expression>) true_statement ;
if (<expression>) true_statement;
else
false_statement;
Contd.
if (<expression1>) true_statement1;
else if (<expression2>) true_statement2;
else
false_statement;
Contd.
always @(*) // using if...else statement
begin
if (s1)
begin
if (s0)
out = i3;
else
out = i2;
end
else
begin
if (s0)
out = i1;
else
out = i0;
end
end
Iterative Statements
While loop
For loop
Repeat loop
Forever loop
times.
While executes a statement until an expression
becomes false. If the expression starts out false, the
statement is not executed at all.
for controls execution of its associated statement(s)
by a three-step process
While Loop
Verilog Code
module count_mod ();
integer count;
initial
begin
count = 0;
while (count < 16)
begin
$display(" Count = %d", count);
count = count + 1;
end
end
endmodule
For Loop
module counter ();
integer count;
initial
for ( count=0; count < 16; count = count + 1)
$display("Count = %d", count);
endmodule
Repeat Loop
module counter ();
integer count;
initial
begin
count = 0;
repeat(16)
begin
$display("Count = %d", count);
count = count + 1;
end
end
endmodule
Example
Mealy FSM
A Mealy machine is a finite-state machine whose
Moore FSM
Moore machine is a finite-state machine whose output
values are determined both by its current state.
Sequence Detector
Design a FSM for detecting sequence
RTL