Architecture of 8086 Microprocessor

Architecture of 8086 Microprocessor

Architecture is divided into two Parts

Bus Interface Unit (BIU)
Execution Unit (EU)
BIU
o Contains the circuit for physical address calculations and a
predecoding instruction byte queue (6 bytes long)
o Makes the systems bus available for external interfacing of
devices
o BIU has a separate adder to perform the procedure for
obtaining a physical address while addressing memory
o Incase of 8085, once the opcode is fetched and decoded,
the external bus remains free for some time, while the
processor internally executes the instruction. The timeslot
is used in 8086 to achieve the overlapped fetch and
execution cycles

Architecture of 8086
o While the BIU fetches the opcode, Execution unit executes
the previously decoded instruction concurrently

BIU along with EU forms a pipeline

BIU manages the complete interface of EU with memory

and I/O devices under the control of timing and control unit
Execution Unit (EU)

Contains the register set of 8086 except segment registers

and IP.

Has a 16 bit ALU to perform arithmetic and logical

operations

16 bit flag reflects the results of execution by ALU

Decoding unit decodes the opcode bytes issued from

instruction byte queue

Timing and Control unit derives the necessary control

signals to execute the instruction opcode

REGISTER ORGANISATION

2 TYPES OF 16 BIT REGISTERS

GENERAL PURPOSE REGISTERS (8 bit)

HOLDS DATA, VARIABLES AND TEMPORARY DATA

SPECIAL FUNCTION REGISTERS

CATEGORIZED AS FOUR TYPES

USED AS SEGMENT REGISTERS, POINTERS,
INDEX REGISTERS or OFFSET STORAGE
REGISTERS

Registers of 8086

GENERAL DATA REGISTERS

AX
BX
CX
DX

AH
BH
CH
DH

AL
BL
CL
DL

AX 16 BIT ACCUMULATOR REGISTER

AH 8 BITS ; AL 8 BITS ; L LOWER ; H - HIGHER
BX USED AS OFFSET STORAGE FOR FORMING
PHYSICAL ADDRESSES IN CASE OF SOME AMS
CX COUNTER (FOR LOOP & STRING OPERATIONS)
DX IMPLICIT OPERAND / DESTINATION

Segment Registers

8086 is segmented Memory

8086 addresses is divided into 16 logical segments (Total of
1MB Memory)
Each segment contains 64KB of Memory
Classified as four types

Code Segment Register (CS) Used for addressing a

memory location in code segment of memory, where
executable program is stored

Data Segment Register (DS) Points to the data segment of

memory, where data is resided

Extra Segment Register (ES) Refers to a segment of

memory which essentially is another data segment of
memory

Stack Segment Register (SS) Used for addressing stack

segment of memory. CPU uses stack for temporarily storing
data

Segment Registers

Physical Address is divided into two parts

Segment Address Contains 16 bit segment base addresses
related to different segments
Offset Any of the pointers and index registers or BX may
contain the offset of the location to be addressed
Advantage of having this is that instead of having a 20 bit
register for physical address, the processor just maintains two
16 bit registers which are within the word length capacity of
the machine

Pointers and Index Registers

Pointers contain offset within the particular segments

Pointers IP, BP and SP usually contain offsets within the code
(JP) and stack (BP & SP) segments
Index registers are used as general purpose registers as well
for offset storage in case of indexed, based indexed and
relative based indexed addressing modes.
Register SI is used to store the offset of source data in data
segment
Register DI is used to store the offset of destination in data or
extra segment
Index registers are used for string manipulations

FLAG REGISTER OF 8086

Functions of 8086 Flags

Carry Flag (CF) - this flag is set to 1 when there is an unsigned

overflow. For example when you add bytes 255 + 1 (result is not in
range 0...255). When there is no overflow this flag is set to 0.

Parity Flag (PF) - this flag is set to 1 when there is even number of
one bits in result, and to 0 when there is odd number of one bits.

Auxiliary Flag (AF) - set to 1 when there is an unsigned overflow

for low nibble (4 bits).

Zero Flag (ZF) - set to 1 when result is zero. For non-zero result
this flag is set to 0.

Sign Flag (SF) - set to 1 when result is negative. When result is

positive it is set to 0. (This flag takes the value of the most
significant bit.)

Functions of 8086 Flags

Trap Flag (TF) - Used for on-chip debugging.

Interrupt enable Flag (IF) - when this flag is set to 1 CPU

reacts to interrupts from external devices.

Direction Flag (DF) - this flag is used by some instructions to

process data chains, when this flag is set to 0 - the processing
is done forward, when this flag is set to 1 the processing is
done backward.

Overflow Flag (OF) - set to 1 when there is a signed

overflow. For example, when you add bytes 100 + 50 (result
is not in range -128...127).

ADDRESSING MODES OF 8086

Immediate Addressing Mode

Direct Addressing Mode
Register Addressing Mode
Register Indirect Mode
Indexed Addressing Mode
Register Relative Addressing Mode
Based Indexed Addressing Mode
Relative Based Indexed Addressing Mode
Intrasegment Direct Mode
Intrasegment Indirect Mode
Intersegment Direct Addressing Mode
Intersegment Indirect Addressing Mode

Addressing Modes of 8086

Immediate Addressing Mode

Immediate data is a part of instruction and appears in the form
of successive byte or bytes
Ex: MOV AX, 0005H
Direct Addressing Mode
16 bit memory address (Offset) is directly specified in the
instruction as a part of it
Ex: MOV AX,[5000H]
Register Addressing Mode
Data is stored in a register and it is referred using the
particular register
Ex: MOV BX,AX

Addressing Modes of 8086

Register Indirect Addressing Mode

The offset address of data is in either BX or SI or DI register
Default segment is either DS or ES

EX:
MOV AX,[BX]
Indexed Addressing Mode
Offset of the operand is stored in one of Index register

DS is default segment for index registers SI and DI

For Strings DS and ES are default segments for SI and DI
EX:
MOV AX, [SI]
Register Relative Addressing Mode
Data is available at an effective address formed by adding an 8
bit or 16 bit displacement with the content of any one of the
registers BX,BP,SI and DI in default segment
EX:
AX,50H[BX]

Addressing Modes of 8086

Based Indexed Addressing Register

Effective address of data is formed by adding content of
base register to content of Index register

Default segment register may be ES or DS

EX:
MOV AX,[BX][SI]
Relative Based Indexed
Effective address is formed by adding an 8 or 16 bit
displacement with the sum of contents of any one of base
registers (BX or BP) and any one of Index registers in a
default segment
EX:
MOV AX,50H [BX] [SI]

Addressing Modes of 8086

Intrasegment Direct Mode

Effective address to which the control is to be transferred is
given by the sum of 8 or 16 bit displacement and current
content of IP

EX: For JMP if signed displacement is 8 bits it is termed as

short jump and if it is 16 bits , it is termed as Long jump
Intrasegment Indirect Mode
The displacement to which the control is to be transferred,
is in the same segment in which the control transfer
instruction lies, but it is passed to the instruction indirectly
Used in Unconditional branch instructions
EX:
JMP [BX];

Addressing Modes of 8086

Intersegment Direct Addressing Mode

Address to which the control is to be transferred is in a
different segment

CS and IP of the destination address are specified directly

in the instruction
EX:
JPM 5000H : 2000H
Intersegment Indirect Addressing Mode
Address to which the control is to be transferred lies in a
different segment and it is passed to the instruction
indirectly
Contents of memory block contains 4bytes (IP(LSB),
IP(MSB), CS(LSB), CS(MSB))

Starting address of the memory block may be referred

using any of the addressing modes except immediate mode
EX:
JMP [2000H]

8086 Microprocessor
Instruction Set of 8086

Structure of an Assembly Language Program

.model small
.stack stack_size
.data

; Select a memory model

; Define the stack size
; Variable and array declarations
; Declare variables at this level

.code
main proc
; Write the program main code here
main endp
;Other Procedures

end main

; Always organize your program

; into procedures
; To mark the end of the source file

Simple Assembly Language Program

.MODEL SMALL
.STACK 64
.DATA
DATA1 DB 52h
DATA2 DB 29h
SUM
DB ?
.CODE
MAIN PROC FAR
MOV AX,@DATA
MOV DS,AX
MOV AL,DATA1
MOV BL,DATA2
ADD AL,BL
MOV SUM,AL
MOV AH,4Ch
INT 21h
MAIN ENDP
END MAIN

Title directive:
The title directive is optional and specifies the title of the
program. Like a comment, it has no effect on the program.

The Model directive:

The model directive gives information on how much memory
the assembler would allocate for the program. This depends on
the size of the data and the size of the program or code.

Segment directives:

Segments are declared using directives. The following

directives are used to specify the following segments:
Stack Segment:

.stack

.stack followed by a value that indicates the size of the stack

Stack addresses are computed as offsets into this segment
Data Segments:

.data

.data followed by declarations of variables or definitions of

constants.
Used to set aside storage for variables.
Constants are defined within this segment in the program
source.
Code Segment:

. code

The code segment contains executable instructions and calls to

procedures.

Data Types and Data Definition

DATA1
DB 25 ; Dec
DATA2
DB 10001001b
DATA3
DB 12h
ORG 0010h
DATA4
DB 2591
ORG 0018h
DATA5
DB ?
This is how data is initialized in the data segment
0000 19
0001 89
0002 12
0010 32 35 39 31
0018

Data Transfer Instructions - MOV

Mnemonic

Meaning

Format

Operation

Flags
affected

Mov

Move

MovD,S

(s)(D)

None

Destination

Source

Memory

Accumulator

Accumulator

Memory

Register

Register

Register

Memory

Memory

Register

Register

Immediate

Memory

Immediate

Seg reg

Reg 16

Seg reg

Mem 16

Reg 16

Seg reg

Memory

Seg reg

NO MOV
Mem
Imm
SegReg

Mem
SegReg
Segreg

EX: MOVAL,BL

Data Transfer Instruction - PUSH

Push word onto stack

Syntax:
push op16
op16: 16-bit register or memory
Action: Push op16 onto the stack
(i.e., SP = SP - 2
then [SS:SP] = op16).
Flags Affected: None
Notes: Pushing and popping of SS and SP are allowed but
strongly discouraged.

Data Transfer Instruction - POP

Pop word from stack

Syntax: pop op16
reg16: 16-bit register or memory
Action: Pop word off the stack and place it in op16 (i.e., op16
= [SS:SP] then SP = SP + 2).
Flags Affected: None
Notes: Pushing and popping of SS and SP are allowed but
strongly discouraged.

Data Transfer Instructions - XCHG

Mnemonic
XCHG

Meaning

Format

Exchange XCHGD,S

Destination

Source

Accumulator

Reg 16

Memory

Register

Register

Register

Register

Memory

Operation

Flagsaffected

(s)(D)

None

Example: XCHG [1234h], BX

NOXCHG
MEMs
SEGREGs

Data Transfer Instructions LEA, LDS, LES

Mnemonic

Meaning

Format

Operation

Flags
affected

LEA

Load
Effective
Address

LEAReg16,EA

EA(Reg16)

None

LDS

Load
Register
AndDS

LDSReg16,MEM32

(MEM32)
(Reg16)

None

(Mem32+2)(DS)
LES

Load
Register
andES

LESReg16,MEM32

(MEM32)
(Reg16)
(Mem32+2)(DS)

LEA SI DATA or MOV SI Offset DATA

None

Examples for LEA, LDS, LES

LES similar to LDS except that it loads ES

Examples for LEA, LDS, LES

DATAXDW1000H
DATAYDW5000H
.CODE
LEASI,DATAX
MOVEDI,OFFSETDATAY;THISISMOREEFFICIENT
LEABX,[DI];ISTHESAMEAS
MOVBX,DI;THISJUSTTAKESLESSCYCLES.
LEABX,DI;INVALID!
LDS BX, [DI];

BX

127A

DI

1000

DS

7A

11000

12

11001

00

11002

30

11003

3000

LESsimilartoLDSexceptthatitloadsES

The XLAT Instruction

Mnemonic

Meaning

Format

Operation

Flags

XLAT

Translate

XLAT

((AL)+(BX)+
(DS)0)
(AL)

None

Example: Assume (DS) = 0300H, (BX)=0100H, and

(AL)=0DH
XLAT replaces contents of AL by contents of memory
location with
PA=(DS)0 +(BX) +(AL)
= 03000H + 0100H + 0DH = 0310DH
Thus
(0310DH) (AL)

Arithmetic Instructions
ADD, ADC, INC, AAA, DAA

If the sum is >9, AH

is incremented by 1

PackedBCD

Arithmetic Instructions
ADD, ADC, INC, AAA, DAA
Mnemonic

Meaning

Format

Operation

Flags
affected

ADD

Addition

ADDD,S

(S)+(D)(D)
carry(CF)

ALL

ADC

Addwith
carry

ADCD,S

(S)+(D)+(CF)(D)
carry(CF)

ALL

INC

Increment
byone

INCD

(D)+1(D)

ALLbutCY

AAA

ASCII
adjustfor
addition

AAA

Ifthesumis>9,AH
isincrementedby1

AF,CF

DAA

Decimal
adjustfor
addition

DAA

AdjustALfordecimal
PackedBCD

ALL

AL=71h
AH=01,AL=07
AX=3137

Examples:
Ex.1ADDAX,2
ADCAX,2

Ex.2INCBX
INCWORDPTR[BX]
Ex.3ASCIICODE0-9=30-39h
MOVAX,38H;(ASCIIcodefornumber8)
ADDAL,39H;(ASCIIcodefornumber9)AL=71h
AAA;usedforadditionAH=01,AL=07
ADDAX,3030H;answertoASCII0107AX=3137
Ex.4ALcontains25(packedBCD)
BLcontains56(packedBCD)
ADDAL,BL
DAA

25
+56
-------7B81

Example:
.MODEL SMALL
.STACK 64
.DATA
DATA1 DQ 548F9963CE7h
ORG 0010h
DATA2 DQ 3FCD4FA23B8Dh
ORG 0020h
DATA3 DQ ?
.CODE
MAIN PROC FAR
MOV AX,@DATA
MOV DS,AX
CLC
MOV SI,OFFSET DATA1
MOV DI,OFFSET DATA2
MOV BX,OFFSET DATA3
MOV CX,04h
BACK: MOV AX,[SI]
ADC AX,[DI]
MOV [BX],AX
ADD SI,2h
ADD DI,2h
ADD BX,2h
LOOP BACK
MOV AH,4Ch
INT 21h; halt
MAIN ENDP
END MAIN

; program that adds two multiword numbers:

;allocate 8 bytes
; allocate 8 bytes

; receive the starting address for DATA

; clear carry
; LEA for DATA1
; LEA for DATA2
; LEA for DATA3

; add with carry to AX

; decrement CX automatically until zero

Arithmetic Instructions SUB, SBB, DEC, AAS, DAS, NEG

CF=1
DAS
AAS
AAS

(AL)difference
(AH)decby1
ifborrow

Arithmetic Instructions SUB, SBB, DEC, AAS,

DAS, NEG
Mnemonic

Meaning

Format

Operation

Flags
affected

SUB

Subtract

SUBD,S

(D)-(S)(D)
Borrow(CF)

All

SBB

Subtract
with
borrow

SBBD,S

(D)-(S)-(CF)(D)

All

(D)-1(D)

AllbutCF

DEC

Decrement DECD
byone

NEG

Negate

NEGD

All

DAS

Decimal
adjustfor
subtraction

DAS

ConverttheresultinALto
packeddecimalformat

All

AAS

ASCII
adjustfor
subtraction

AAS

(AL)difference
(AH)decby1ifborrow

CY,AC

Examples:DAS

Borrow1fromAH

Examples:DAS
MOV BL, 28H
MOV AL, 83H
SUB AL,BL; AL=5BH
DAS
; adjust as AL=55H

MOV AX, 38H

SUB AL,39H; AX=00FF
AAS ; AX=FF09 tens complement of -1(Borrow one from AH )
OR AL,30H ; AL=39

Assume (BX)=003AH, what is the result of executing the

instruction
NEG BX

(BX)=0000000000111010
2s comp = 1111111111000110 = FFC6H
(CF)=1

Example
32-bit subtraction of two 32 bit numbers X and Y that are stored
in the memory as
X = (DS:203h)(DS:202h)(DS:201h)(DS:200h)
Y = (DS:103h)(DS:102h)(DS:101h)(DS:100h)
The result X - Y to be stored where X is saved in the memory
MOV SI, 200h
MOV DI, 100h
MOV AX, [SI]
SUB AX, [DI]
MOV [SI], AX ;save the LS word of result
MOV AX, [SI] +2
SBB AX, [DI]+2
MOV [SI] +2, AX
Ex. 12 34 56 78 23 45 67 89 = EF EE EE EE

MultiplicationandDivision

Multiplication and Division

Multiplication and Division

Multiplication
(MUL or IMUL)

Multiplicant

Operand
(Multiplier)

Result

Byte*Byte

AL

Register or
memory

AX

Word*Word

AX

Register or
memory

DX :AX

Dword*Dword

EAX

Register or
memory

EAX :EDX

Division
(DIV or IDIV)

Dividend

Operand
(Divisor)

Quotient:
Remainder

Word/Byte

AX

Register or
Memory

AL : AH

Dword/Word

DX:AX

Register or
Memory

AX : DX

Qword/Dword

EDX: EAX

Register or
Memory

EAX : EDX

Multiplication and Division Examples

Ex1: Assume that each instruction starts from these values:
AL = 85H, BL = 35H, AH = 0H
1. MUL BL AL . BL = 85H * 35H = 1B89H AX = 1B89H
2. IMUL BL AL . BL = 2S AL * BL = 2S (85H) * 35H
= 7BH * 35H = 1977H 2s comp E689H AX.
3. DIV BL

AX
BL

0085 H
35 H

0085 H
AX
4. IDIV BL BL = 35H =

= 02 (85-02*35=1B)
AH

AL

1B 02

AH

AL

1B

02

Ex2:

AL = F3H, BL = 91H, AH = 00H

1. MUL BL AL * BL = F3H * 91H = 89A3H AX = 89A3H
2. IMUL BL AL * BL = 2S AL * 2S BL = 2S (F3H) * 2S(91H) =
0DH * 6FH = 05A3H AX.

00 F 3H
00 F 3H
AX
3.IDIV BL
=
=
= 2 (00F3 2*6F=15H)

BL

AH

AL

15

02

2' S (91H )

6 FH

AH
POS
NEG 2s(02)=FEH 15

NEG

00 F 3H
AX
4. DIV BL
=
= 01(F3-1*91=62)
91
H
BL

AL

FE

AH

AL

62

01

RQ

Ex3:

AX= F000H, BX= 9015H, DX= 0000H

1. MUL BX = F000H * 9015H =

DX
8713

AX
B000

2. IMUL BX = 2S(F000H) * 2S(9015H) = 1000 * 6FEB =

DX

AX

06FE

B000

F 000 H
3. DIV BL =
= B6DH More than FFH Divide Error.
15 H

2' S ( F 000 H ) 1000 H

4. IDIV BL
=
= C3H > 7F Divide Error.
15 H
15 H

Ex4:

AX= 1250H, BL= 90H

AX 1250 H
POS
POS
1250 H
1250 H
1. IDIV BL
=
=
=
=
=
BL
NEG 2' sNEG 2' s (90 H )
70 H
90 H
=29H(Q)(125029*70)=60H(REM)
29H(POS)2S(29H)=D7H

RQ
60H
D7H

RQ
1250 H
AX
20H
2.DIVBL==20H1250-20*90=50H 50H
90 H
BL
AHAL

Logical Instructions

Logical Instructions
Mnemonic

Meaning

Format

Operation

Flags Affected

AND

Logical AND

AND D,S

(S) (D) (D)

OR

Logical Inclusive OR

OR D,S

(S)+(D) (D)

XOR

Logical Exclusive OR

XOR D,S

NOT

LOGICAL NOT

NOT D

(S) + (D)(D)
_
(D) (D)

OF, SF, ZF, PF, CF

AF undefined
OF, SF, ZF, PF, CF
AF undefined
OF, SF, ZF, PF, CF
AF undefined
None

Destination

Source

Register
Register
Memory
Register
Memory
Accumulator

Register
Memory
Register
Immediate
Immediate
Immediate

Destination
Register
Memory

Logical Instructions
AND
Uses any addressing mode except memory-to-memory and
segment registers
Especially used in clearing certain bits (masking)
xxxx xxxx AND 0000 1111 = 0000 xxxx
(clear the first four bits)
Examples:
AND BL, 0FH
AND AL, [345H]
OR
Used in setting certain bits
xxxx xxxx OR 0000 1111 = xxxx 1111
(Set the upper four bits)

 XOR
Used in inverting bits
xxxx xxxx XOR 0000 1111 = xxxxxxxx
-Example: Clear bits 0 and 1, set bits 6 and 7, invert bit 5 of
register CL:
AND CL, OFCH ;
1111 1100B
OR CL, 0C0H
;
1100 0000B
XOR CL, 020H ;
0010 0000B

Shift Instructions

Shift Instructions
Mnemonic

Meaning

Format

Operation

Flags Affected

SAL/SHL

Shift arithmetic
Left/shift
Logical left

SAL/SHL D,Count

Shift the (D) left by the

number of bit positions
equal to count and fill
the vacated bits
positions on the right
with zeros

CF,PF,SF,ZF
AF undefined
OF undefined if count 1

SHR

Shift logical
right

SHR D,Count

Shift the (D) right by the

number of bit positions
equal to count and fill
the vacated bits
positions on the left
with zeros

CF,PF,SF,ZF
AF undefined
OF undefined if count 1

SAR

Shift arithmetic
right

SAR D,Count

Shift the (D) right by the CF,PF,SF,ZF

number of bit positions
AF undefined
equal to count and fill
OF undefined if count 1
the vacated bits
positions on the left
with the original most
significant bit

Shift Instructions
Destination

Count

Register

Register

CL

Memory

Memory

CL

 Ex.
; Multiply AX by 10
SHL AX, 1
MOV BX, AX
MOV CL,2
SHL AX,CL
ADD AX, BX

Ex. What are the results of

SAR CL, 1
if CL initially contains B6H? DBH

Ex. What are the results of

SHL AL, CL
if AL contains 75H and CL contains 3? A8H

Rotate Instructions

Rotate Instructions
Mnemonic

Meaning

Format

Operation

Flags Affected

ROL

Rotate left

ROL D,Count

Rotate the (D) left by the

number of bit positions
equal to Count. Each bit
shifted out from the left
most bit goes back into the
rightmost bit position.

CF
OF undefined if count 1

ROR

Rotate right

ROR D,Count

Rotate the (D) right by the

number of bit positions
equal to Count. Each bit
shifted out from the
rightmost bit goes back into
the leftmost bit position.

CF
OF undefined if count 1

RCL

Rotate left
through
carry

RCL D,Count

Same as ROL except carry

is attached to (D) for
rotation.

CF
OF undefined if count 1

RCR

Rotate right
through
carry

RCR D,Count

Same as ROR except carry

is attached to (D) for
rotation.

CF
OF undefined if count 1

Rotate Instructions

Destination

Count

Register

Register

CL

Memory

Memory

CL

Ex. What is the result of ROL BTRE PTR [SI], 1

if SI is pointing to a memory location that contains 41H?

(82H)

Example
Write a program that counts the number of 1s in a
byte and writes it into BL
DATA1 DB 97 ; 61h
SUB BL, BL ; clear BL to keep the number of 1s
MOV DL, 8 ; Counter
MOV AL, DATA1
AGAIN: ROL AL,1 ; rotate left once
JNC NEXT ; check for 1
INC BL ; if CF=1 then add one to count
NEXT: DEC DL ; go through this 8 times
JNZ AGAIN ; if not finished go back
NOP

Flag Control Instructions

The 8086 microprocessor has a set of lags to either monitor the

status of executing instructions or control options available in
its operation.
The instruction set includes a group of instructions that when
executed directly affect the state of the flags. The instructions
are:
Load AH from flags (LAHF)
Store AH into flags (SAHF)

Clear carry (CLC)

Set carry (STC)
Complement carry (CMC)
Clear interrupt (CLI)
Set interrupt (STI)

Control Transfer or Branching Instructions

Transfer the flow of execution of the program to a new address

specified in the instruction directly or indirectly
Classified as two types
Unconditional Control Transfer (Branch) Instructions
o Execution control is transferred to the specific location
independent of any status
Conditional Control Transfer (Branch) Instructions
o Control is transferred to the specified location provided
the result of the previous operation satisfies a particular
condition, otherwise execution continues in normal flow
sequence

Unconditional Branch Instructions

CALL: Unconditional Call : Procedure in ALP

Used to call a subroutine from main program
Address is specified directly or indirectly based on type of
addressing mode
Classified as Near Call (+/- 32K displacement) and Far
Call (Anywhere outside the segment)
On execution, this instruction stores the incremented IP
and CS onto the stack and loads the CS and IP registers
For Near call it pushes only IP and for Far call it pushes
both CS and IP on to the stack

Unconditional Branch Instructions

RET: Return from Procedure

Executed at the end of each Procedure
When executed, the previously stored content of IP and CS
along with flags are retrieved into the CS, IP and Flag
registers from stack and execution of the main program
continues

Classified into 4 types based on the type of procedure

o Return within the segment
o Return within the segment adding 16 bit immediate
displacement to the SP contents
o Return Intersegment
o Return Intersegment adding 16 bit immediate
displacement to the SP
contents

Unconditional Branch Instructions

INT N: Interrupt Type N

256 interrupts in 8086
When INT N is executed, the TYPE byte is multiplied by 4
and the contents of IP and CS of ISR will be taken from
hexadecimal multiplication (N`4) as offset address and
0000 as segment address
For Execution of this instruction IF has to be enabled

INTO: Interrupt on Overflow

Executed, when the overflow flag OF is set

New contents of IP and CS are taken from the address
0000:0010

Unconditional Branch Instructions

JMP: Unconditional Jump

IRET: Return from ISR

Unconditionally transfers the control of execution to the

specified address using an 8-bit or 16-bit displacement
No flags are affected
Classified as 3 types

Before transferring call to IRET, the IP, CS and flag

register are stored on to stack to indicate the location from
where the execution is to be continued, after the ISR
executed

Loop: Loop Unconditionally

Execute the part of program from the label or address

specified in the instruction upto the loop instruction, CX
number of times

Conditional Branch Instructions Jump Instructions

Conditional Branch Instructions Loop Instruction

Assembler Directives

DB: Define Byte

Used to reserve byte or bytes of memory locations in the
available memory
Directs the assembler to allocate the specified number of
memory bytes to the said data type that may be a constant
EX:
RANKS
DB 01H, 02H, 03H, 04H
DW: Define Word
Functions similar to DB but makes the assembler reserve
the number of memory words instead of bytes
EX:
WORDS
DW 1234H, 4567H, 78ABH, 045CH

Assembler Directives

DQ: Define Quad Word

Used to direct the assembler to reserve 4 words
May initialize with the specific values
DT: Define Ten Bytes
Directs the assembler to define the specified variable
requiring 10 bytes for its storage and initialize the 10 bytes
with the specified values
Assume: Assume Logical segment Name
Used to inform the assembler, the names of the logical
segments to be assumed for different segments used in
program
Must at the start of each program

Assembler Directives

END: End of Program

Marks the end of ALP

When encountered it ignores the source lines available later

ENDP: End of Procedure

All the statements appearing in the same module after this

instruction will be stopped abruptly
ENDS: End of Segment

Marks the end of a logical segment

Logical segments are assigned with names using ASSUME

directive

Names appearing with ENDS as prefixes to mark the end of those

particular segment

Assembler Directives

EVEN: Align on Even Memory Address

Every Assembler first initializes a location counter
Updates the location counter to the next even address, if the
current location counter contents are not even, and assigns
the following routine or variable or constant to that address
EQU: Equate
Used to assign a label with a value or a symbol
Reduces the recurrence of the numerical values or
constants in a program code

Each recurring value is assigned a label and that label is

used throughout the program
EXTRN: External and Public: Public
Informs the assembler that the names, procedures and
labels declared after this directive have already been
defined in some of the ALP modules

Assembler Directives

GROUP: Group the related segments

Used to form logical groups of segments with similar

purpose or type
Informs the assembler to form a logical group of following
segment names
PROGRAM GROUP
CODE, DATA, STACK
LABEL: Label
Used to assign a name to the current content of the location
counter
Length: Byte length of a Label
Not available for MASM
Refers to the length of data array or string
MOV CX, LENGTH
ARRAY

Assembler Directives

LOCAL
The Labels, Variables, constants or procedures declared
LOCAL are to be used only by that particular module
Same label can serve different purposes for different
modules of a program
NAME: Logical Name of a Module
Used to assign the name to an ALP module
Module can now be referred as the declared name
OFFSET: Offset of a Label
Used with arrays, strings, labels and procedures to decide
their offsets in their default segments

Assembler Directives

ORG: Origin

Directs the assembler to start the memory allotment for the particular
segment, block or code from the declared address in the ORG
statement

ORG 200H
PROC: Procedure

Marks the start of a named procedure in the statement

Near and Far specify the types of a procedure

PUBLIC

Used along with EXTRN

Informs the assembler that the labels, constants or procedures declared

public can be accessed by other assembly modules to form their codes

Assembler Directives

SEGMENT: Logical Segment

Marks the starting of a logical segment

Started segment is also assigned a name i.e., Label

SEGMENT and ENDS must bracket each logical statement

EXE.CODE
SEGMENT CODE
EXE.CODE
ENDS
SHORT

Indicates to the assembler that only one byte is required to

code the displacement for a jump

This method of jumping save memory

JMP
SHORT
LABEL
TYPE

Directs the assembler to decide the data type of the

specified label and replaces the TYPE label by the decided
data type

MOV AX, TYPE STRING

Assembler Directives

GLOBAL
Labels, Variables, Constants or procedures declared
GLOBAL can be used by other modules of the program
ROUTINE
PROC GLOBAL
FAR PTR
Indicates that the label following this directive is not
available within the same segment and the address of the
label is of 32 bits
JMP
FAR PTR
Label
NEAR PTR
Indicates that the label following this directive is in the
same segment and needs only 16 bit to address it
JMP
NEAR PTR Label

Procedure

Subroutines in a ALP
May require input data or constants for their execution
If interactive it may directly accept inputs from input devices
Techniques to pass data to procedures in ALP
Using Global declared variable
Using registers of CPU architecture
Using memory locations (Reserved)
Using Stack
Using PUBLIC & EXTRN

Procedure

The syntax for procedure declaration:

name PROC
; here goes the code
; of the procedure ...
RET
name ENDP
name - is the procedure name, the same name should be in the
top and the bottom, this is used to check correct closing of
procedures.
Probably, you already know that RET instruction is used to
return to operating system. The same instruction is used to
return from procedure (actually operating system sees your
program as a special procedure).
PROC and ENDP are compiler directives, so they are not
assembled into any real machine code. Compiler just remembers
the address of procedure.
CALL instruction is used to call a procedure.

MACROS
Process of assigning a label or macro name to a string

Process of assigning a label or macro name to a string

Similar to Subroutines
The complete code of instructions string is inserted at each place
where the macro name appears
Does not utilize the service of stack
Can be defined anywhere in the program
Uses the directives MACRO and ENDM
The label prior to MACRO directive is called Macro name, which
should be used in actual program
ENDM marks the ends the instructions sequence assigned with
macro name
EX: DISPLAY MACRO
MOV AX, SEG MSG
MOV DS, AX
MOV DX, OFFSET MSG
MOV AH, 09H
INT 21H
ENDM

MACROS

Can be used in Data segment

Can be used to represent statements and directives
Can be called by quoting its name along with any values to be
passed to the macro
Programmer specifies the parameters of the macro those are to
be changed each time the macro is called
There may be more than one parameter in a macro definition
All Parameters are defined sequentially
A macro may be defined in another macro and may be called
from inside a macro