LAYOUT DESIGN

RULES

Introduction

Complexity of various processes increases in

VLSI.
Relationships between different photo
masks cant be interpreted easily.
To overcome this we define certain layout
rules
They act as communication link between circuit
designer and process engineer.
Used to obtain a circuit with optimum yield in area
as small as possible.
Reliability of circuit should not be compromised.

Need of design rules

Arises due to manufacturing problems like:

Variations in material deposition, temperature and
oxide thickness.
Impurities
Variations across wafer

These leads to problems like:

Transistor problems:
Variations in Vth
Changes in source/drain diffusion overlap.
Variations in substrate.

Contd..
Wiring problems
Diffusion
Poly,metal: variation in height and width
Shorts and opens

Oxide problems
Variation in height
Lack of planarity

Via problems:
Via may not be cut all the way through
Undersize via has too much resistance
Too large a via can create short

Contd..
For reducing these problems design rules
specify to a designer certain geometric
constraints on layout artwork.
Consists of minimum width and minimum
spacing constraints between objects of
same or different layers.

Contd..

Figure showing different types of

via:through,blind,buried

Types of design rules

Design rules address mainly two issues:

Geometrical reproduction of features.
Interaction between different layers.

Linear scaling possible only over limited

range of dimensions.
Scalable design rules are conservative.
Two of the design approaches:

Scalable design rules(-based rule)

All rules are defined based on a single parameter .
Rules are chosen such that layout is portable.

Contd..
Scaling can be easily done by changing value.

Absolute design rules(-based design rules)

Design rules are expressed in absolute dimensions.
Scaling and porting is more demanding.
More complex for deep submicron levels.

Fundamental unity in set of design rules is

minimum line width.

Layer representation
Visualization of all mask levels that are used
in fabrication levels become inhibited with
increasing process complexity.
Layer concept translates these masks to a
set of conceptual layout levels.
From designers view point all CMOS
designs have following entities:

Two different substrates and wells.

Diffusion regions
Transistor gate electrodes

Contd..
Metal interconnect layers
Interlayer contacts and via layers.

The layers for typical CMOS processes in

various figures are represented in terms of:
A color scheme
Other color schemes to differentiate different
CMOS structures.
Varying stipple patterns
Varying line styles

Stick diagram
Another popular method of symbolic design.
A freehand sketch of layout.
Means of capturing topography and layer
information using simple diagrams.
Stick diagrams convey layer information
through colour codes (or monochrome
encoding).
Acts as an interface between symbolic
circuit and the actual layout.

Contd..

Colored lines are used to represent various

process layers like diffusion,metal and
polysilicon.
Indicates relative positioning of design
components
Shows all the components and vias.
Helps plan layout and routing.
Absolute co-ordinates of elements determined
by editor using a compactor.
Compactor ensures that final layout is
physically correct.

Disadvantages

Does not show:

Exact placement of components

Transistor size
Wire lengths,wire widths etc.
Any other low level details like parasitics.

Stick diagram notations

Metal 1
poly
ndiff
pdiff

Can also draw

in shades of
gray/line style.

Rule 1.
When two or more sticks of the same type
cross or touch each other that represents
electrical contact.

Rule 2.
When two or more sticks of different type
cross or touch each other there is no
electrical contact.
(If electrical contact is needed we have to show the connection
explicitly).

Rule 3.
When a poly crosses diffusion it represents
a transistor.

Note: If a contact is shown then it is not a transistor.

Rule 4.
In CMOS a demarcation line is drawn to
avoid touching of p-diff with n-diff. All
pMOS must lie on one side of the line and
all nMOS will have to be on the other side.

How to draw a stick

diagram
VDD

Gnd

NOR gate in CMOS

Implementing an
expression
Power

Out

C
B
Ground