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SYSTEM LEVEL DESIGN ISSUES

CONTENT
Soft IP vs Hard IP
Design for timing closure : Logic design

issues
Design for verification
System interconnect and on-chip
buses
Design for low power
Design for test: Manufacturing test
strategies

Soft IP vs Hard IP
Synthesis, placement, and routing then

maps the RTL to gates, and the gates


to GDSII. The process of mapping from
RTL to GDSII is called hardening.
The integration of the hardened block
into the final chip is just the same as
integrating any other hard IP, such as a
memory.

The advantage of pre-hardened blocks

is that they go through physical design


once,and then can be used many
times.
Can be used without modification in
many different chips, since timing
closure is completely predictable.
The advantage of synthesis-based
design over full custom is that it
provides
a
much
faster
implementation path for new designs.

Design for timing closure :


Timing and synthesis issues include
Logic
synchronous
asynchronous design,
designorissues
clock and reset schemes,
selection of synthesis strategy.

and

1. Interfaces and Timing


Closure
The proper design of block interfaces can
make timing closureboth at the block level
and system level.
As blocks become larger, the variance
between the average delay and the actual
delay on worst case wires can become quite
large.
Timing-driven place and route tools can help
deal with some of these timing problems.

Macro Interfaces

Subblock Interfaces

2. Synchronous vs.
Asynchronous Design Style
Rule The system should be synchronous

and register (flip-flop) based. Latches


should be used only to implement small
memories or FIFOs. These memories and
FIFOs should be synchronous and edge
triggered.

3. Clocking
SoC

designs almost always require


multiple clock domains.
The high-speed bus and the low-speed bus
will have separate clocks.
Shut down certain blocks at certain times
to conserve power by shutting down the
clock to those blocks.

Clock Planning
Rule
The system clock generation and control

logic should be separate from all functional


blocks of the system.
The number of clock domains and clock
frequencies must be documented.

Clock Delays for Hard


Blocks
Once the insertion delay can address in

either of two ways:


Eliminate the delay using a PLL.
Balance the clock insertion delay with the
clock delay for the rest of the logic.

4. Reset
Rule The basic reset strategy for the chip must

be documented.
Synchronous reset:
Advantage: Is easy to synthesize.
Disadvantage: Requires a free-running clock.
Asynchronous reset:
Advantage: Does not require a free-running clock.
Uses separate input on flop, so it does not affect
flop data timing.
Disadvantage: Is harder to implement.
Makes static timing analysis and cycle-based
simulation more difficult.

Design for Verification:


Verification Strategy

The objective of verification is to assure that the

block or chip being verified is 100% functionally


correct.
Best strategy for minimizing defects is to do
bottom-up verification.
Rule
The system-level verification strategy must be
developed and documented before macro
selection or design begins.
The macro-level verification strategy must be
developed and documented before the design of
macros and major blocks for the chip begins.

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