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Verilog Tutorial

By Trung Vu Nguyen

Introduction
Verilog is a Hardware Description Language
(HDL) used to model electronic systems.
Verilog is used in design and verification of
digital circuits at register-transfer level.
C-like syntax
Easy to learn & use
The Verilog HDL is both a behavioral and
structural language.
Case sensitive language.

Where is Verilog used in design flow

To write design entry and make test env.

Behavioral vs. structural


language
Behavioral language: describe at
algorithm level to functional level.
Structural language: describe detail
structure of components.

Behavioral vs. structural


language
Example: Full adder
Function:
Add two number A and B
regarding to carry-in (Cin)
value.
Output is Sum (S) and Carry-out (Cout).

Behavioral language
module FA_behaviour( sum,co,a,b,ci);
input a,b,ci;
output reg sum,co;
always@(a or b or ci)
{co,sum} = a + b + ci;

endmodule

Structural language

Design method
Hierarchy Design(Structural
language)
Abstraction Design (Behavioral
language)

Hierarchy Design
Top Down Methodology
Bottom Up Design Methodology

Top Down Design


Methodology
Top level module

Sub
Module 1
Cell
1

Cell
2

Sub
Module 2
Cell
1

Cell
2

Sub
Module 3
Cell
1

Cell
2

Sub
Module 4
Cell
1

Cell
2

Bottom Up Design
Methodology
Top level module

Sub
Module 1
Cell
1

Cell
2

Sub
Module 2
Cell
1

Cell
2

Sub
Module 3
Cell
1

Cell
2

Sub
Module 4
Cell
1

Cell
2

Abstraction Design
Behavioral level :

count <= count + 1;

Data flow level : assign a = b & c;


Gate level : and a1(y ,a ,b);
Switch level: pmos p1 (out,pwr,in);
nmos n1 (out,gnd,in);

Module
Module STARTING:
module name
portlist (Testbench doesnt have portlist).
port declaration (compulsory)

Module BODY:
declaration of internal variables (compulsory for reg variables)
instantiation of other modules
continuous statements (combinational logics)
procedural blocks (sequential logics)
Initial blocks (testbench only)
Task and functions (optional)

Module ENDDING

Sample Module
Module name: adder
(case sensitive)

Module STARTING

portlist

module adder (a, b, sum, cin, cout);


input wire a;
input wire b;
input wire cin;
Port declaration
output reg sum;
output reg cout;
assign {cout, sum} = a + b + cin;
Continuous statement

Module BODY

Module ENDDING

always @(a or b or cin) begin

end

procedural statement

always @(posedge clk or negedge


reset) begin
.
end
endmodule

Countinuous vs. procedural


statements

module adder (a, b, sum, cin, cout); Continuous statement:


Sensitive list indicates trigger sources
input wire a;
for code execution between begin and
input wire b;
end.
input wire cin;
output reg sum;
In this example, any state transition of
output reg cout;
or b or cin will cause the execution
assign {cout, sum} = a + b + cin; of code between begin and end
always @(a or b or cin) begin

end
always @(posedge clk or negedge
reset) begin
.
end
endmodule

Procedural statement:
Statements which use clock to
trigger
updating process.
In this example, code between
begin
and end will be executed every
rising
edge of clock (posedge) or falling

Instantiation
Instantiation is used to create an
object for the design and replicates
There are two ways to instantiate an
instance of a module: named base
and ordered base.

Verilog keywords
module design_name (

endmodule

input_name, output_name);

D- Flip Flop
- Basic store element in sequential logic.
- Updates output (Q) state with state of input
(D) when event (rising or falling edge of
clock) occurs.
- Reset signal will set output (Q) to 0.