Chapter 9: Input/Output

The Architecture of Computer Hardware

and Systems Software:
An Information Technology Approach
3rd Edition, Irv Englander
John Wiley and Sons 2003
Wilson Wong, Bentley College
Linda Senne, Bentley College

Basic Model
Processing speed or program execution
determined primarily by ability of I/O
operations to stay ahead of processor.

Input

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Process

Output

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I/O Considerations
Speed Issues

CPU operates at speeds much faster than the fastest I/O device
Devices operate at different speeds
Bursts of data
Block data transfer required for some devices

Coordination

Several devices perform I/O simultaneously

Unexpected input
Various input formats
Status information needed for each device

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I/O Device Interface Issues

Different formats

parallel interface
serial interface

Buffering of data
Burst vs. stream
Different control requirements
electromechanical

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Examples of I/O Devices

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Simple I/O Configuration

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I/O Modules Functions

Recognizes messages from device(s) addressed to it
and accepts commands from the CPU
Provides a buffer where the data from memory can be
held until it can be transferred to the disk
Provides the necessary registers and controls to
perform a direct memory transfer
Physically controls the device
Copies data from its buffer to the device/from the
CPU to its buffer
Notifies with interrupts
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Input/Output Modules
Programmed I/O
CPU controlled I/O

Interrupt Driven I/O

External input controls

Direct Memory Access Controllers

Method for transferring data between main
memory and a device that bypasses the
CPU
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Programmed I/O
I/O data and address registers in CPU
One word transfers
Address information for each I/O device
LMC I/O capability for 100 devices

Full instruction fetch/execute cycle

Primary use:
keyboards
communication with I/O modules (see DMA)
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Programmed I/O

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Programmed I/O Example

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Programmed I/O Example

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Interrupts
Signal that causes the CPU to alter its
normal flow on instruction execution
frees CPU from waiting for events
provides control for external input

Examples

unexpected input
abnormal situation
illegal instructions
multitasking, multiprocessing

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The CPU - The Interrupt Cycle

Fetch / Execute cycle
Interrupt cycle
START
Fetch Next
Instruction
HALT

Execute
Instruction

Interrupts Disabled

Check/Process
Interrupt

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Interrupt Terminology
Interrupt lines (hardware)
Interrupt request
Interrupt handlers
Program that services the interrupt
Also known as an interrupt routine

Process Control Block (PCB)

Located in a part of memory known as the stack
area
All registers of a program are saved here before
control is transferred to the interrupt handler
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Interrupt Terminology
Servicing the interrupt
suspends program in progress
saves pertinent information including last
instruction executed and data values in
registers in the PCB (process control
block)
branches to interrupt handler

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Servicing an Interrupt

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Use of Interrupts
Notify that an external event has occurred
real-time or time-sensitive

Signal completion
printer ready or buffer full

Allocate CPU time

time sharing

Indicate abnormal event (CPU originates for

notification and recovery)
illegal operation, hardware error

Software interrupts
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Multiple Interrupts
Identifying devices
Polling (checking for input in rotation)
Vectored interrupts (include address of
interrupting device)

Interrupt priorities
Loss of data vs. task completion

Maskable (disabled) interrupts

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Vectored Interrupts

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Polled Interrupts

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Multiple Interrupts Example

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Direct Memory Access

Transferring large blocks of data

Direct transfer to and from memory
CPU not actively involved in transfer itself
Required conditions for DMA
The I/O interface and memory must be connected
The I/O module must be capable of reading and
writing to memory
Conflicts between the CPU and the I/O module
must be avoided
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DMA Instruction Set

Application program requests I/O service
from operating system

privileged instructions

To initiate DMA, programmed I/O is used to

send the following information:
1.
2.
3.
4.

location of data on I/O device

the starting location in memory
the size of the block
read/write

Interrupt to CPU upon completion

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DMA Initiation and Control

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Basic CPU-Memory-I/O Pathway*

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Bus Configuration

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Bus Characteristics
Data width in bits carried simultaneously
Throughput, i.e., data transfer rate in bits
per second
Point-to-Point vs. Multipoint
Parallel vs. Serial
Use
Distance
Protocol
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Bus Hierarchy
Processor bus: on-chip
Cache bus (backside bus)
Memory bus (front-side bus)
connects the memory subsystem and processor

Local I/O bus

high-speed bus used to connect performance
critical peripherals to memory and processor
Examples: PCI, VESA Local Bus

Standard I/O bus

connects slower peripherals (ISA) to Local I/O bus
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Wintel Bus Systems

ISA: Industry Standard Architecture

MCA: Micro Channel Architecture
EISA: Extended Industry Standard Architecture
Local Bus
PCI: Peripheral Component Interconnect (also Apple, Sun,
Compaq Alpha Server)
VLB: VESA (Video Electronics Standards Association) Local Bus

AGP: Accelerated Graphics Port

Point-to-point channel from graphics controller to main
memory
Co-exists with PCI

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Compaq 7000 and 10000

System Architecture

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External Interface Buses and Ports

Parallel port
Serial port
RS-232C and RS-422 buses

SCSI
Small Computer System Interface

USB, USB-2
Universal Serial Bus

IEEE 1394
Firewire
i.link
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SCSI Bus
ANSI standard but multiple variations
Really an I/O bus rather than simple interface
Supports multiple devices from a single SCSI port

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USB
Multipoint bus
Hubs provide
multiple connection
points for I/O devices
Supports 127 devices

Topology Example

Root
Hub
Hub

Hub

Hub

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USB and FireWire (IEEE 1394)

Both serial, multipoint bus specifications
Add/remove devices w/o powering
down
Packet protocol for isochronous data
transfer
Isochronous: delivery at regular time
intervals
Guarantee specified throughput
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USB vs. FireWire

USB: slow to medium speed data
transfer applications, i.e., storage
devices
12 Mbits/sec

USB-2: high-speed data transfer

480Mbits/sec

FireWire: high-speed data transfer, i.e.,

full motion video with sound
400 Mbits/sec to 3.2 Gbits/sec
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Typical FireWire Configuration

Network-like characteristics
Device controllers independent

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Channel Architecture
Used in IBM mainframe computers
Channel subsystem
Separate I/O processor that serves as a CPU for
I/O operations
Channel control words
Programs that transfer data between memory and
an I/O device using DMA

Subchannels
Connected to a control unit module through one or
more channel paths
Similar role to a device controller
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I/O Channel Architecture

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