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MINI STEREO
DIGITAL AUDIO
PROCESSOR
(MSDAP)
_______________________________________
Chintan Modi(chm130430)
Ujas Patel(unp130030)
OBJECTIVES
GENERAL DESCRIPTION
where:
FEATURES
A system clock (Sclk) of 26.88MHzand a data
clock (Dclk) of 768 KHz is used.
16 bit audio input and 40 bit audio output.
Supports dual channel serial inputs with the
Dclk.
Supports dual channel serial outputs with the
Sclk.
Automatic sleep mode when 800 consecutive zero
inputs are obtained.
State 0 (Initialization):
FSM enters this state when Start signal is high.
The system initializes.
Remains in this state as long as the Start is high.
When the initialization process is complete, the chip enters state 1.
Remains in state 1 waiting for the rj values to appear on the input channels.
When the Frame signal is set high, the chip enters state 2.
State 6 (working): input samples are read by the chip and stored in memory.
The convolution is computed and output data is sent out serially once the computation is completed.
InReady signal remains high during this state.
If Reset_n is detected low, the chip enters state 7.
If the chip detects 800 consecutive zero samples at both the input channels simultaneously, it enters
state 8.
State 7(clearing):
Data memory is cleared.
Once the clearing process is completed, the chip goes to state 5.
As long as the Reset_n is low, the chip remains in this state.
State 8 (sleeping):
If 800 consecutive zeros are detected on both the input channels chip enters this state.
If a non-zero sample is detected on any of the input channels, the chip transitions to state 6.
If Reset_n is detected low, the chip enters state 7.
MSDAP receives the control signals and the input data from the
controller.
MSDAP block processes the data and sends the output samples to
the controller block.
SYSTEM SPECIFICATION
Pin
Sclk
Dclk
Frequency
System clock is operating at a frequency of 26.88MHz.
During this clock Chip implements Linear Convolution .
INPUT PINS
Pin
Pin Number
Description
Sclk
Dclk
Start
15
Reset_n
Frame
20
InputL
17
InputR
16
When Reset_n is set low, the chip begins to reset. The outputs, inputs
and counters are set to zero.
Frame is used to align the serial coefficients, input and output samples.
In case of first bit Frame is set high for one Dclk cycle after receiving
the first bit then it is set low.
The left channel coefficients are given through InputL at the negative
edge of Dclk.
The right channel coefficients are given through InputR at the negative
edge of Dclk.
OUTPUT PINS
Pin
Pin Number
Description
InReady
12
OutReady
11
OutputL
OutputR
10
SIGNAL FORMAT
Sign Bit
MSB
Time Slots
LSB
13-bits
15
Input Data
Unused Bits
0 to 7
8 to 15
RJ Data
Unused Bits
MSB
Rj data
LSB
0 to 7
9 to 14
15
Coefficients Data
INPUT CONVERSION
Input Data received as 16 bit is converted to 40 bits.
16 zeros are padded at the end of Input data, as filter
order is 256(maximum 16 shifts possible)
Sign Extension is done on First 8 bits
For Coeffecients, Last 8 bits indicate the maginitude and
the 9th bit is the sign bit.Other bits are discarded
For Rj, Last 8 bits indicate the magnitude and rest are
discarded
The first bit (MSB) is received when the Frame is detected high on
the rising edge of the Dclk.
Hence the Frame signal denotes the beginning of the input data
stream.
After the first bit is received the Frame goes low. InReady is high
during this time denoting that the chip is ready to receive data.
Output frame starts with the rising edge of the Frame and lasts 40
Sclk cycles.
Description
InputL/R
Frame
Dclk
state
data/R
trigrj
triguj
readrj
readuj
MEMORY
Signals
Description
Sclk
Start
data/R
readrj
Readuj
state
storerj
storeuj
addr_rj/rjR
addr_uj/ujR
Rj/rjR_data
uj/ujR_data
Description
Sclk
Frame
OutReady
outY/YR
DATA MEMORY
Signals
Description
state
Frame
Dclk
trigx
readx
tempX/XR
It is used in ALU
InputL/R
sleepof
CONTROLLER
Signals
Description
Start
InReady
Sclk
Frame
Reset_n
Sleepof
trigrj
Trigger rj memory
triguj
storerj
storeuj
trigsleep
trigx
resetflag
algoinit
ALU
Signals
Description
Sclk
Start
q/qR
b/bR
outflag
Y/YR
trigsleep
algoinit
resetflag
State0 is an initialization phase. When the initialization process is completed, the MSDAP enters State 1.
MSDAP starts reading the Rj values and the InReady signal continues to remain high in State 2. One by
one bit is read of first Rj on data. If all Rj values have been loaded, the MSDAP enters State 3
In State 3 the MSDAP is waiting to receive the coefficients. In this state InReady is set high. If Frame signal
is detected to be high, MSDAP enters State 4.
In State 4, the chip starts reading the coefficients. In this the InReady signal remains high.
Once all the coefficients have been loaded, the MSDAP enters State 5.
In State 5, the MSDAP is waiting to receive the data. In this state InReady is set high. If Frame is detected
to be high, the chip enters State 6. It receives the data
CONCLUSION
REFERENCE
1)
2)
3)
4)
5)
http://www.emmelmann.org/Library/Tutorials/docs/verilog_ref_gu
ide/vlog_ref_top.html
THANK YOU