THE SCAN-PATH

SCAN-PATH TECHNIQUE
TECHNIQUE
THE
FOR TESTABLE
TESTABLE SEQUENTIAL
SEQUENTIAL
FOR
CIRCUIT DESIGN
DESIGN
CIRCUIT
Presented by,
Presented by,
Lavanyashree B. J
Lavanyashree B. J
LVS07
LVS07
VLSI Design & Embedded Systems
VLSI Design & Embedded Systems

INDEX
Combinational and sequential circuits
Scan path technique
Modified sequential circuit
Raceless D-type flip flop
Configuration of logic card
Advantages and Disadvantages
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COMBINATIONAL AND SEQUENTIAL

CIRCUITS
Complexity testing sequential circuits due to
feedback loops
Placement of the circuit in a known state.

Timing problems in general

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SCAN PATH TECHNIQUE

In 1975, Nippon electric company introduced a design for testability
techniques called SCAN PATH .

Scan is ability to shift into or out of any state

Scan-path design is to reduce test generation complexity for circuit
containing storage devices and feedback path with combinational logic.
The philosophy is to divide & conquer with the purpose to :
1. Set any internal state easily
2. Observe any state through a distinguishing sequence
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Continued..

Modified general sequential

circuit has following properties:
Circuit can easily be set to
any desired internal state
Circuit has distinguishing
sequence

Fig1: A sequential circuit

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Continued..

When
C=0 Normal mode
C=1 Shift Register
Uses double throw switch

A
B

Double Throw-Switch has a

contact that can be connected
to either of two other
contacts.

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Fig2: A realization for the Doublethrow Switch

Continued..

Procedure for testing circuit is

1. Set C=1 to switch circuit to
shift register mode
2. Check operation as shift register
by scan in inputs ,scan-out
outputs and clock
3. Set initial state of shift register
4. Set C=0 to return to normal
mode
5. Apply test input pattern to
combinational logic
6. Set C=1 ting state to return to
shift register mode
7. Shift out final state while setting
the starting state for the next
test.
8. Go toLVS07,VLSI
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Fig3: Modified sequential

circuit
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Continued..

Raceless D-type flip flop

Scan-out

Normal operation:
C2=1 & C1=0
So data is latched to D1
When C1=1
Output of L1 is latched into L2
Scan in operation:
C2=0
Test input is applied at D2.
When C2=1
Output of L1 is latched into L2

Fig 4: Raceless flip flop with scan path

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Continued..

Configuration of Logic card

Here flip flops are connected
as shift register

Scan-out

Scan-in

Each card has one scan path.

Fig 5: Configuration of logic card

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Advantages and Disadvantages

Advantages:
Design automation
High fault coverage; helpful in diagnosis
Easy to generate test pattern

Disadvantages:
Large test data volume and long test time
Requires extra pins or gates for transformation

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THANK YOU..
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