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Lecture 8
Finite State Machines
State Diagrams,
State Tables,
Algorithmic State Machine (ASM) Charts,
and VHDL code
ECE 448 FPGA and ASIC Design with VHDL
Required reading
P. Chu, FPGA Prototyping by VHDL Examples
Chapter 5, FSM
S. Brown and Z. Vranesic,
Fundamentals of Digital Logic with VHDL Design
Chapter 8, Synchronous Sequential Circuits
Sections 8.1-8.5
Chapter 8.10, Algorithmic State Machine
(ASM) Charts
ECE 448 FPGA and ASIC Design with VHDL
Datapath
vs.
Controller
Datapath
(Execution
Unit)
Control Inputs
Control
Signals
Controller
(Control
Unit)
Status
Signals
Data Outputs
Status Outputs
Controller
Controller can be programmable or non-programmable
Programmable
Has a program counter which points to next instruction
Instructions are held in a RAM or ROM externally
Microprocessor is an example of programmable
controller
Non-Programmable
Once designed, implements the same functionality
Another term is a hardwired state machine or
hardwired instructions
In the following several lectures we will be focusing
on non-programmable controllers.
ECE 448 FPGA and ASIC Design with VHDL
Interface
Pseudocode
Datapath
Block
diagram
VHDL code
ECE 448 FPGA and ASIC Design with VHDL
Controller
Block
diagram
VHDL code
State diagram
or ASM chart
VHDL code
9
10
Manual Optimization/Minimization Is
Practical for Small FSMs Only
ECE 448 FPGA and ASIC Design with VHDL
11
Moore FSM
Output Is a Function of a Present State Only
Inputs
Next State
function
Next State
clock
reset
Present State
Present State
register
Output
function
ECE 448 FPGA and ASIC Design with VHDL
Outputs
12
Mealy FSM
Output Is a Function of a Present State and Inputs
Inputs
Next State
function
Next State
clock
reset
Present State
Present State
register
Output
function
ECE 448 FPGA and ASIC Design with VHDL
Outputs
13
State Diagrams
14
Moore Machine
transition
condition 1
state 1 /
output 1
transition
condition 2
state 2 /
output 2
15
Mealy Machine
transition condition 1 /
output 1
state 2
state 1
transition condition 2 /
output 2
16
17
18
1
S0 / 0
reset
Meaning
of states:
S0: No
elements
of the
sequence
observed
0
S1 / 0
0
S1: 1
observed
S2 / 1
S2: 10
observed
19
1/0
S0
reset
Meaning
of states:
1/0
S1
0/1
S0: No
elements
of the
sequence
observed
S1: 1
observed
20
clock
input
Moore
Mealy
S0
S1
S2
S0
S0
S0
S1
S0
S0
S0
21
22
FSMs in VHDL
Finite State Machines Can Be Easily
Described With Processes
Synthesis Tools Understand FSM Description
if Certain Rules Are Followed
State transitions should be described in a process
sensitive to clock and asynchronous reset signals
only
Output function described using rules for
combinational logic, i.e. as concurrent statements
or a process with all inputs in the sensitivity list
23
Moore FSM
process(clock, reset)
Inputs
Next State
function
Next State
clock
reset
Present State
Register
Present State
Output
function
Outputs
concurrent
statements
ECE 448 FPGA and ASIC Design with VHDL
24
Mealy FSM
process(clock, reset)
Inputs
Next State
function
Next State
clock
reset
Present State
Present State
Register
concurrent
statements
ECE 448 FPGA and ASIC Design with VHDL
Output
function
Outputs
25
1
S0 / 0
0
S1 / 0
reset
S2 / 1
26
27
28
1/0
S0
reset
1/0
S1
0/1
29
30
31
32
33
0 (False)
Condition
expression
1 (True)
Conditional outputs
or actions (Mealy type)
34
State Box
State box represents a state.
Equivalent to a node in a state diagram or a
row in a state table.
Contains register transfer actions or output
signals
Moore-type outputs are listed inside of the
box.
It is customary to write only the name of the
signal that has to be asserted in the given
state, e.g., z instead of z<=1.
Also, it might be useful to write an action to be
taken, e.g., count <= count + 1, and only later
translate it to asserting a control signal that
causes a given action to take place (e.g.,
enable signal of a counter).
ECE 448 FPGA and ASIC Design with VHDL
State name
Output signals
or actions
(Moore type)
35
Decision Box
Decision box
indicates that a
given condition is to
be tested and the
exit path is to be
chosen accordingly
The condition
expression may
include one or more
inputs to the FSM.
ECE 448 FPGA and ASIC Design with VHDL
0 (False)
Condition
expression
1 (True)
36
Conditional outputs
or actions (Mealy type)
37
38
A z = 0
B z = 0
w =0
w =1
w =0
C z = 1
w =1
39
Next state
Present
state w = 0 w = 1
A
B
C
A
A
A
B
C
C
Output
z
0
0
1
40
w
1
B
w
1
C
z
41
: IN STD_LOGIC ;
: IN STD_LOGIC ;
: IN STD_LOGIC ;
: OUT STD_LOGIC ) ;
42
43
44
Reset
w = 1 z = 0
w = 0 z = 0
w = 1 z = 1
w = 0 z = 0
45
w
1
B
z
46
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ) ;
47
48
49
g1
r1
r2
Arbiter
g2
g3
r3
clock
ECE 448 FPGA and ASIC Design with VHDL
50
Reset
Idle
0xx
1xx
gnt1g1 =1
x0x
1xx
01x
gnt2g2 =1
xx0
x1x
001
gnt3g3 =1
xx1
ECE 448 FPGA and ASIC Design with VHDL
51
Reset
Idle
r1
r1
gnt1 g1 = 1
r1
r2
r 1r 2
gnt2 g2 = 1
r2
r3
r 1r 2 r 3
gnt3 g3 = 1
r3
ECE 448 FPGA and ASIC Design with VHDL
52
Idle
r1
1
gnt1
1
g1
r2
gnt2
g2
r3
r1
r2
1
1
gnt3
g3
r3
53
: IN
: IN
: OUT
STD_LOGIC ;
STD_LOGIC_VECTOR(1 TO 3) ;
STD_LOGIC_VECTOR(1 TO 3) ) ;
54
55
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