Latch versus Register

Latch
stores data when
clock is low

Register
stores data when
clock rises

D Q

D Q

Clk

Clk

Clk

Clk

Latches
Positive Latch
In

Negative Latch

Out

In

CLK

CLK

clk

clk

In

In

Out

Out
Out
Out
stable follows In

Out
Out
stable follows In

Out

Latch-Based Design
N latch is transparent
when = 0

P latch is transparent
when = 1

N
Latch

Logic

Logic

P
Latch

Timing Definitions
CLK
t
tsu
D

thold

DATA
STABLE
tc 2

Register

t
q

DATA
STABLE

Q
CLK

Positive Feedback: Bi-Stability

V i1

V o1 =V i2

Vi2

V o1

V o2 =V i1

V i1

V o2

A
V i2 =V o1
C
B
V i1 =V o2

V o2

V i2 5 V o1

V i2 5 V o1

Meta-Stability

B
V i1 5 V o2

B
V i1 5 V o2

Gain should be larger than 1 in the transition reg

Writing into a Static Latch

Use the clock as a decoupling signal,
that distinguishes between the transparent and opaque states
CLK

CLK
Q
CLK

D
CLK

CLK

Converting into a MUX

Forcing the state

(can implement as NMOS-only)

Mux-Based Latches

Negative latch
Positive latch
(transparent when CLK=
0)
(transparent
when CLK= 1

1
D

0
CLK

Q Clk Q Clk In

1
CLK

Q Clk Q Clk In

Mux-Based Latch
CLK

Q
CLK
D

CLK

Mux-Based Latch

CLK

QM

CLK

QM
CLK

CLK

NMOS only

Non-overlapping clocks

Master-Slave (EdgeTriggered) Register

Slave
Master
0
1
D

QM

D
QM
Q

CLK
CLK

Two opposite latches trigger on edge

Also called master-slave latch pair

Master-Slave Register
Multiplexer-based latch pair

I2

CLK

T2

I3

I5

T4

I4

T3

QM
I1

T1

I6

Clk-Q Delay
2.5

Volts

CLK

1.5

0.5

2 0.5
0

tc 2

tc 2

q(lh)

0.5

1
1.5
time, nsec

q(hl)

2.5

Setup Time
3.0

3.0
Q

2.5

QM
D

2.0
Volts

Volts

2.0
1.5

2.5

CLK

1.0
I 2 2 T2

0.5

CLK

1.0

QM

0.5

0.0
2 0.5
0

1.5

I 2 2 T2

0.0
0.2

0.4
0.6
time (nsec)

0.8

(a) Tsetup5 0.21 nsec

2 0.5
0

0.2

0.4
0.6
time (nsec)

0.8

(b) Tsetup5 0.20 nsec

Reduced Clock Load

Master-Slave Register
CLK
D

T1
CLK

CLK
I1
I2

T2
CLK

I3
I4

Avoiding Clock Overlap

X

CLK

CLK
Q

A
B

CLK

CLK
(a) Schematic diagram

CLK

CLK
(b) Overlapping clock pairs

Other Latches/Registers: C MOS

2

CLK

VDD

VDD

M2

M6

M4

D
CLK

M3
M1

CLK
X

M8
Q

CL1

CLK

M7

CL2

M5

Master Stage

Keepers can be added to make circuit pseudo-static

Insensitive to Clock-Overlap

VDD

VDD

VDD

VDD

M2

M6

M2

M6

M4

0
X

M8
Q

D
1

M1
(a) (0-0) overlap

M5

M3

Q
1

M1
(b) (1-1) overlap

M7
M5

Other Latches/Registers:
TSPC
VDD

VDD

VDD

VDD

Out
In

CLK

CLK

In

CLK

CLK

Positive latch
Negative latch
(transparent when CLK= 1)
(transparent when CLK= 0)

Including Logic in TSPC

VDD

VDD

VDD
In1

PUN

VDD
In2

Q
In

CLK

CLK

PDN

Example: logic inside the latch

Q
CLK

CLK

In1

AND latch

TSPC Register
VDD
M3

CLK

VDD

VDD

M6

M9
Y

CLK

M2

M1

CLK

M5

M4

Q
Q

CLK

M8

M7

Pulse-Triggered Latches
An Alternative Approach

Ways to design an edge-triggered sequential ce

Pulse-Triggered Latch

Master-Slave
Latches
Data

Clk

L1

L2

D Q

D Q

Clk

Clk

Data
Clk

L
D Q
Clk

Pulsed Latches
Hybrid Latch Flip-flop (HLFF), AMD K-6 and K-7 :
CLK

P1

P3

M6

M3
D

M2
M1

P2

M5
M4