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VHDL
Behavioral Modeling
Spring 2014 Semester
dataflow
structural
behavioral
Sequential statements
Components and
interconnects Registers
Shift registers
Counters
synthesizable
State machines
Concurrent
statements
Behavioral Design/Modelling
Anatomy of a Process
The process statement is a concurrent statement , which
delineates a part of an architecture where sequential statements
are executed.
Syntax
[label:] process [(sensitivity list )]
declarations
begin
sequential statements
end process [label];
Concurrent VS sequential
Every statement inside the architecture body is
executed concurrently, except statements
enclosed by a process.
Process
Statements within a process are executed sequentially.
Result is known when the whole process is complete.
You may treat a process as one concurrent statement in
the architecture body.
Process(sensitivity list): when one or more signals in the
sensitivity list change state, the process executes once.
Process should either have sensitivity list or an explicit
wait statement. Both should not be present in the same
process statement.
6
Process contd..
The order of execution of statements is the
order in which the statements appear in
the process
All the statements in the process are
executed continuously in a loop .
The simulator runs a process when any one
of the signals in the sensitivity list changes.
For a wait statement, the simulator
executes the process after the wait is over.
A
B
Cin
Sum
Cout
ENTITY
ENTITYfull_adder
full_adderIS
IS
PORT
PORT((A,
A,B,
B,Cin
Cin::IN
INBIT;
BIT;
Sum,
Sum,Cout
Cout::OUT
OUT
BIT
BIT);
);
END
ENDfull_adder;
full_adder;
Full Adder
Architecture
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
for Sum:
Cin (I.e. Carry In):
AB 0
1
00 0
1
01 1
0
11 0
1
10 1
0
A
B
Cin
Sum
Cout
Carry:
Carry:
PROCESS(
PROCESS( A,
A, B,
B, Cin)
Cin)
BEGIN
BEGIN
Cout
Cout <=
<= (A
(A AND
AND B)
B) OR
OR
(A
AND
Cin)
OR
(A AND Cin) OR
(B
(B AND
AND Cin);
Cin);
END
END PROCESS
PROCESS Carry;
Carry;
Complete Architecture
ARCHITECTURE
ARCHITECTURE example
example OF
OF full_adder
full_adder IS
IS
--- Nothing
Nothing needed
needed in
in declarative
declarative block...
block...
BEGIN
BEGIN
Summation:
Summation: PROCESS(
PROCESS( A,
A, B,
B, Cin)
Cin)
BEGIN
BEGIN
Sum
Sum <=
<= AA XOR
XOR BB XOR
XOR Cin;
Cin;
END
END PROCESS
PROCESS Summation;
Summation;
Carry:
Carry: PROCESS(
PROCESS( A,
A, B,
B, Cin)
Cin)
BEGIN
BEGIN
Cout
Cout <=
<= (A
(A AND
AND B)
B) OR
OR
(A
(A AND
AND Cin)
Cin) OR
OR
(B
AND
Cin);
(B AND Cin);
END
END PROCESS
PROCESS Carry;
Carry;
END
END example;
example;
VHDL Sequential
Statements
The if statement
Syntax
if condition1 then
statements
[elsif condition2 then Priority
statements]
[else
statements]
end if;
An if statement selects one or none of a sequence of
events to execute . The choice depends on one or more
conditions.
Carry:
Carry: PROCESS(
PROCESS( A,
A, B,
B, Cin)
Cin)
BEGIN
BEGIN
IF
IF (( AA == 1
1 AND
AND BB == 1
1 )) THEN
THEN
Cout
Cout <=
<= 1;
1;
ELSIF
ELSIF (( AA == 1
1 AND
AND Cin
Cin == 1
1 ))
THEN
THEN
Cout
Cout << == 1;
1;
ELSIF
ELSIF (( BB == 1
1 AND
AND Cin
Cin == 1
1 ))
THEN
THEN
Cout
Cout <=
<= 1;
1;
ELSE
ELSE
Cout
Cout <=
<= 0;
0;
END
END IF;
IF;
END
END PROCESS
PROCESS Carry;
Carry;
Priority Encoder
clk
w
a
b
c
y
priorit
y
Sig1 = 2 + 3 = 5
Sig2 = 1
Sig3 = 2
Sum = 1 + 2 + 3 = 6
var1 = 2 + 3 = 5
var2 = 5
var3 = 5
Sum = 5 + 5 + 5 =
15
For Loops
Add Function
WHILE LOOP :
Syntax :
loop_label: while condition loop
<sequence of statements>
end loop loop_label
Statements are executed continuously as long as
condition is true.
Has a Boolean Iteration Scheme.
Condition is evaluated before execution.
Use of others
Null statement
null_statement::=
[ label : ] null ;
The null - statement explicitly prevents any action from being carried out.
This statement means do nothing.
This command can, for example, be used if default signal assignments have
been used in a process and an alternative in the case statement must not change
that value.
architecture rtl of ex is
begin
p1: process (a)
begin
q1<=0;
q2<=0;
q3<=0;
case a is
when 00 =>
q1<=1;
when 10 =>
q2<=1;
q3<=1;
when others => null;
end case;
end process;
end;
Wait statement
wait_statement::=
[ label : ] wait [ sensitivity_clause ]
[ condition_clause ]
[ timeout_clause ] ;
Examples:
wait ;
The process is permanently interrupted.
wait for 5 ns ;
The process is interrupted for 5 ns.
wait on sig_1, sig_2 ;
The process is interrupted until the value of one of the
two signals changes.
wait until clock = '1' ;
The process is interrupted until the value of clock is 1.
In the first example the process will be triggered each time that signal a or b
changes value (aevent or bevent)
Wait on a,b; has to be placed at the end of the second example to be identical
with the first example because all processes are executed at stat-up until they
reach their first wait statement.
That process also executed at least once, which has sensitivity list and
there is no changes in the values of the list members
If a wait on is placed anywhere else, the output signals value will be different
when simulation is started.
If a sensitivity list is used in a process, it is not permissible to use a wait
command in the process.
It is permissible, however, to have several wait commands in the same process.
Wait until a=1; means that, for the wait condition to be satisfied and
execution of the code to continue, it is necessary for signal a to have an event,
i.e. change value, and the new value to be 1, i.e. a rising edge for signal a.
Wait on a,b; is satisfied when either signal a or b has an event (changes value).
Wait for 10 ns; means that the simulator will wait for 10 ns before continuing
execution of the process.
The starting time point of the waiting is important and not the actual changes of any
signal value.
It is also permissible to use the wait for command as follows:
constant period:time:=10 ns;
wait for 2*period;
The wait alternatives can be combined into: wait on a until b=1 for 10 ns;,
but the process sensitivity list must never be combined with the wait
alternatives
Example: wait until a=1 for 10 ns;
The wait condition is satisfied when a changes value or after a wait of 10 ns
(regarded as an or condition).
type a: in bit; c1, c2, c3, c4, c5, c6, c7: out bit;
Example 1
process (a)
begin
c1<= not a;
end process;
Example 5
process
begin
c5<= not a;
wait until a=1;
end process;
Example 2
process
begin
c2<= not a;
wait on a;
end process;
Example 3
process
begin
wait on a;
c3<= not a;
end process;
Example 6
process
begin
c5<= not a;
wait for 10 ns;
end process;
Example 4
process
begin
wait until a=1;
c4<= not a;
end process;
Example 7
process
begin
c5<= not a;
wait until a=1 for 10 ns;
end process;
Simulation results
10
20
30
40
50
C1
C2
C3
C4
C5
C6
C7
10 ns
20 ns
60
time [ns]
The majority of synthesis tools only accept a sensitivity list being used for
combinational processes, i.e. example 1, but not example 2, can be synthesized.
But some advanced systems accept example 2, while example 3 is not
permitted in synthesis.
Example 4 is a clocked process and results in a D-type flip-flop after synthesis.
Examples 3 and 5 can only be used for simulation, and not for design.
The wait command is a sequential command, it is not permissible to use wait in
functions, but it can be used in procedures and processes.
Attributes
Value kindA simple value is returned.
Function kindA function call is performed to
return a value.
Signal kindA new signal is created whose value is
derived from another signal.
Type kindA type mark is returned.
Range kindA range value is returned.
Array Attributes
Signal Attributes
Attributes associated with signals
that return a value
Timing Model
VHDL uses the following simulation cycle to
model the stimulus and response nature of
digital hardware
Start Simulation
Delay
Update Signals
Execute Processes
End Simulation
Delay Types
All VHDL signal assignment statements
prescribe an amount of time that must transpire
before the signal assumes its new value
This prescribed delay can be in one of three
forms:
Transport -- prescribes propagation delay only
Inertial -- prescribes propagation delay and minimum input pulse width
Delta -- the default if no delay time is explicitly specified
Input
delay
Output
Transport Delay
Transport delay must be explicitly specified
I.e. keyword TRANSPORT must be used
Input
Output
Input
Output
0
35
10
15
20
25
30
Inertial Delay
Provides for specification propagation delay and input
pulse width, i.e. inertia of output:
target <= [REJECT time_expression] INERTIAL waveform;
Input
Output
Input
Output
0
35
10
15
20
25
30
Input
Output
0
35
10
15
20
25
30
Delta Delay
Default signal assignment propagation delay if no delay
is explicitly prescribed
VHDL signal assignments do not take place immediately
Delta is an infinitesimal VHDL time unit so that all signal
assignments can result in signals assuming their values at a
future time
E.g.
Output <= NOT Input;
-- Output assumes new value in one delta cycle
Simulation Example
ENTITY dtype IS
PORT(clk, d, clr, pre : IN std_logic;
q, n_q : OUT std_logic);
END dtype;
ARCHITECTURE behav OF dtype IS
SIGNAL temp_q : std_logic; -- internal signal
BEGIN
PROCESS (clk, clr, pre)
BEGIN
IF clr = 1 THEN -- clear operation
temp_q <= 0;
ELSIF pre = 1 THEN -- preset operation
temp_q <= 1;
ELSIF clkEVENT AND clk = 1 THEN -- clock
temp_q <= d;
END IF;
END PROCESS;
q <= temp_q;
n_q <= NOT temp_q;
END behav;