Low Power Verification

- Jyothi Sreenivasulu

NLP: Native Low Power

Simulation w.r.t voltage

Low-power verification is the explosion in scope and complexity caused
by low-power design techniques.
It is no longer sufficient to simulate a design assuming voltage to be a constant.
Most designs today have voltage changes during operation, such as when a design
enters a low-Vdd standby state or utilizes DVS modes. (other many states like.,
Sleep, Hibernate,etc)
This requires simulation to understand voltage levels to accurately resolve signal
values and timing.
Power state transitions require understanding of the dynamic nature of voltage and
its effect on logic;
outputs become a function of not only the logical value on the inputs, but also the
voltage levels of those values.
VCS equips with MVSIM (Multi voltage simulator) or VCS-MXNLP

Inputs for NLP

Power intent formats:

Unified Power Format. An IEEE 1801 Standard

By the Silicon Integration Initiatives (Si2s) Common Power Format

(CPF)

Verification flow using UPF

Incremental process to make Golden UPF

Golde
n RTLUPF

DC
Outpu
t UPF

- UPF is Input to LP verification from

RTL
- UPF becomes Golden when
completely
validated and verified

- Golden UPF is performed for P&R with

proper library cell mapping for all the
strategy cells
- This is called DC output Golden UPF which
is used for Netlist Sims

VCS Tool and NLP support

Color structures of Different Strategies

Automated Flow

Power Intent Infrastructure..

Components of UPF
Power Domain:
Groups of elements which share a common set of power supply requirements

Power Supply Network:

Abstract description of power distribution (ports, nets, sets & switches)

Power State Table:

The legal combinations of states of each power domain

Isolation Strategies:
How the interface to a power domain should be isolated when its primary power supply is removed

Retention Strategies:
What registered state In a power domain should be retained when its primary power supply is removed

Level Shifter Strategies:

How signals connecting power domains operating at different voltages should be shifted

Repeater Strategies:
How domain ports should be buffered

Power Switch Strategies:

Switching voltage to other domain

Low Power Design Techniques

Clock tree optimization and clock gating
In normal operation:
The clock signal continues to toggle at every clock cycle.
There is a large source of dynamic power waste.

In clock gating Operation:

Clock gating ensures power is not dissipated during the idle time when blocks
are off.
Clock gating can occur at the leaf level (at the register) or higher up in the
Low Power
Architectu Design
Verificati Implementatio
clock
tree.
Technique
re
on
n
Clock Gating

Low

Low

Low

Low

Verification effort:
Focus on developing
assertions

verification

methods.,

like

Low Power Design Techniques Cont..

Multi-supply voltage (MSV or voltage islands)

Multi-supply voltage techniques operate different blocks at different voltages.

MSV techniques require level shifters on signals that go from one voltage level to another.
Without level shifters, signals that cross voltage levels will not be sampled correctly.

Low Power
Technique

Architect
ure

Design

Verificatio
n

Implementati
on

MSV

High

Medium

Low

Medium

1.2V
1.2V
1.0V
1.0V

Verification effort:

Focus on developing verification plan for

voltage level crossing on
power domains

0.9V
0.9V

Low Power Design Techniques Cont..

Dynamic voltage scaling (DVS) & Dynamic voltage and frequency

scaling (DVFS)
DVFS techniques reduce power consumption on the fly by scaling down
the voltage (and frequency) based on the requirement.
DVFS is one of the only techniques that is highly effective on both
dynamic
static power.
Low
Power and
Architectur
Design
Verification Implementa
Technique

DVS &
DVFS

High

tion
High

High

High

PWR
PWR
CTRL
CTRL

1.0V
1.0V

Verification effort:

Focus on developing verification plan for

voltage level crossing on
power domains

0.9-1.2V
0.9-1.2V

0.9V
0.9V

Low Power Design Techniques Cont..

Power shut-off (PSO) [or power gating]
PSO-Also called Power Gating technique
Switches off power to parts of the design when these blocks are not in use.
It eliminate up to 90 percent of the leakage current.
Power gating is employed to shut off power in standby mode.
A specific power-down sequence is needed, which includes isolation on
signals from the shut-down domain.
PSO needs proper sequence of all the low power techniques involved

1.2V
OFF
1.2V

1.0V
1.0V

0.9V
0.9V

Power

Gating(Shutdown)

Low Power
Technique

Architecture

Design

Verification

Implementa
tion

DVS & DVFS

High

High

High

High

Verification effort:
Focus on developing verification plan for power
down sequence
and its sub-sequences
which
Power Gating
are tiedwith
together
state Retention

1.2V
RET
1.2V

1.0V
1.0V

0.9V
0.9V

LP Strategies and Sequences

Isolation
If the driving domain can be OFF when the receiving domain is ON,
the receiving domain needs to be protected by isolation.
Isolation cells are specially designed for low short circuit current
when input is at threshold voltage level.
Can hold a logic 1 or 0, or can hold the signal value latched at the
time of the power-down event. (called clamping to known value., normally
reset values)
Verification Effort: High
Isolation cells
must
have power
during block power down periods.
Follow
thethemselves
Isolation sequence
and missing
ISO
VCS provides Automated assertions
Custom assertions requirements extraction
Verify at RTL level and also check the correct
isolation lib cells at Gate level

LP Strategies and Sequences Cont..

Retention
In LP cases, the state of key control flops needs to be retained during power-off.
To speed power-up recovery, state retention power gating (SRPG) flops can be
used.
Retains their state while the power is off, provided that specific control
requirements
are met. (Which are called Save and Restore signaling)
Cell libraries today include such special state retention cells.
Storing mechanism:
-

SAVE signal saves the register data into the shadow register prior

to
Verification
High
power-down Effort:
and

Follow the Retention sequence

The RESTORE Signal restores the data after power-up
VCS provides Automated assertions
Custom assertions requirements extraction
A key area of verification is checking that these
library-specific requirements have been satisfied
and the flop will actually retain its state.
Develop the test cases to cover the functionality
with the target design under full retention

LP Strategies and Sequences Cont..

Retention Continuation
MVSIM-NLP has capabilities to verify retention at various stages of the design
flow like RTL and netlist.
At RTL stage where retention registers are typically not implemented yet,
MVSIM-NLP will infer the retention registers based on the retention specification
in the UPF.
MVSIM-NLP will automatically save and restore the states based on the save
and restore signal specification.

LP Strategies and Sequences Cont..

Level Shifter
Level shifting is a technique to convert a signal driven by one set of primary rails
to another set of primary rails
Level shifters are two types of voltage rails converters between multi-voltage
domains
1. HIGH to LOW
2. LOW to HIGH

Enable level shifters (ELS): Acts as a LS and ISO (LS+ISO)

o The power switching can be combined with multi-voltage
operation.
o
The
Verification
interface cells
Effort:
between
Low different blocks must perform

Follow
theshifting
ELS sequence
(If enabled)
both
level
and isolation
functions.
VCS provides Automated assertions
Custom assertions requirements extraction
Validation is required for LS if any structural
errors are happened. (missing LS, or
redundant LS.,etc)

LP Strategies and Sequences Cont..

Power Switch
A power switch (header or footer) is added to supply rails to shut-down logic.
Any use of power switching requires isolation cells where signals leave a powered-down
block and enter a block that is always on (or currently powered up).
Also called power gating technique.
It contains control signals and multi voltages which passes proper voltage to other domain.
Power switch also contains delay specific to ON/OFF power domain voltage.
They are three types of Switches:
o Header switch
o Footer Switch
o Both

Verification Effort: High

Follow the power down/up sequence

Follow the ISO and RET sequences
VCS provides Automated assertions
Custom assertions requirements extraction
Power state or modes verification

LP Strategies and Sequences Cont..

Power State Table(PST)
In the UPF, PST is a collection of all possible power states for all input supply
nets/ports of a design.
If the PST is over constrained, it will result in structural redundancy in
implemented design while a under constrained PST will result in structural violations.
UPF does not provide the capabilities to describe PST at abstract design level to
describe
the golden rules for merging, state completion and coverage semantics.

LP Verification Efforts

Strategies verification
LP coverage
Power model development
Project setups

LP Assertions

Tool Assertions
Generic Assertions

LP Directed Tests