AXI_ASSERTIONS

Madhusudhana Reddy

Mindlance Technologies

Agenda

Protocol with assertions

Assertions points with protocol

AXI Protocol with Assertions

Protocol with Assertions

Specifications

Normal functionality

Features

Relation bw Inputs

Relation bw Outputs

Input & Output Relations

Legal & Illegal scenarios

Combination of one to all

Warnings

Error Scenarios
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Assertions development areas

Global signals

Reset of DUT

Default values

Range of values ( Input & Output)

Signal transitions

State transitions

Reserved values

Assertion usage in DV

Part of assertions

Valid signal assertion

Continue
Property dut_on(
@(posedge ACLK ) ARESETn |=> VALID );
Endproperty

Reset

The AXI protocol includes a single active LOW reset

signal, ARESETn. The reset signal can be asserted
asynchronously, but deassertion must be synchronous
after the rising edge of ACLK.

Property reset_sig(clk,ARESETn);

@(posedge clk) !ARESETn|=>ARESETn[*1:$] ##1 !

ARESETn;
endproperty

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Reset with READY AND VALID SIGNALS

During reset the following interface requirements apply:

A master interface must drive ARVALID, AWVALID,

and WVALID LOW

A slave interface must drive RVALID and BVALID LOW.

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Property Rst_rv(
@(posedge ACLK) !ARESETn |-> (
AWVALID==0 &&
WVALID==0 &&
ARVALID==0 &&
BVALID== 0
)
)
Assert_Rst_rv: assert property( Rst_rv)
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VALID CONTROL & ADDRESS DATA

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VALID Control information

Property valid_data(
@(posedge ACLK) AWVALID |-> (
$stable(AWID) &&
$stable(AWLEN) &&
$stable(AWPROT)
)
)

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15

16

17

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Default value checking

assert property ( disable iff( !ARESETn )

a==x &&
b==y &&
c==$past(c)

);

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Data bus width

Data bus(Read,write), that can be 8, 16, 32, 64, 128,

256, 512, or 1024 bits wide

Assert property (

@(posedge ACLK) ($countones(DATABUS_WIDTH)==1 ||

$countones(DATABUS_WIDTH)==1)
)

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AWLENGTH min and max values

property xxx_range(int min,int max);

@(posedge ACLK)
AWVALID->( AWLEN>=min && AWLEN <=max);
Endproperty
Range_assert:assert property(xxx_range(0,15));

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Valid transaction

property valid_trans(valid,ready);

@(posedge ACLK)
(valid && ready) ;
Endproperty

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Inside

Property range_inside;
@(posedge ACLK) arlen inside{1,16};

Endproperty
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ERROR

Except (@(posedge ACLK) WID=AWID ) $error(IDs

are mismatch)

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Property valid_check(
@(posedge ACLK)
ARVALID|->$stable(ARADDR)
Endpropoerty
Assert_valid_check:assert property ( valid_check);

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Property valid_check(
@(posedge ACLK) (ARVALID==1 && ARREADY==1) |>$stable(ARADDR)
Endpropoerty
Assert_valid_check:assert property ( valid_check);

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Property Rdata_check(
@(posedge ACLK) (RVALID==1 && RREADY==1)
|->$stable(RDATA)
Endpropoerty
Assert_rdata_check:assert property
( Rdata_check);

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Burst_Completion_check

Property last_tr_check(
@(posedge ACLK) (RVALID==1 && RREADY==1
&& RLAST==1) |->$stable(RDATA)
Endpropoerty
Assert_rdata_check:assert property
( last_tr_check);

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Property total_tr(
@(posedge ACLK)
(ARADDR && ARVALID) |=> ##3 (ARVALID && RREADY) ##3
( ARVALID && RREADY && $stable(RDATA) ##1 ( ARVALID
&& RREADY && $stable(RDATA) ( ARVALID && RREADY &&
RLAST && $stable(RDATA) )
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Out of transaction

Sequence s;
(ARVALID ##1 ARREADY)[*2] ;
End sequence
Property out_tr( @(posedge ACLK)
ARVALID|->s; Endproperty

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Property xxx

@(posedge ACLK) ( RLAST && RVALID && RREADY ) |

=>##[1:4](RVALID && RREADY)
endproperty

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WRITE BURST

Property xyz

@(posedge ACLK)
(AWVALID && AWREADY)|=>[*1:$] ($stable(WDATA))[->1:4];
endproperty

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WRITE BURST

Sequence s;

(AWVALID && AWREADY);

Endsequence
Propert wr_burst(
@(posedgeACLK) AWVALID|=>[*1:$] (WVALID ==1 &&
WREADY==1 &&$stable(WDATA))[->1:4]
endproperty

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WRITE BURST

Sequence s;

(AWVALID && AWREADY)

Endsequence
Propert wr_burst(

@(posedgeACLK) AWVALID=>[*1:$] (WVALID ==1 &&

WREADY==1 &&$stable(WDATA))[->1:$]##1 (BRESP==OKAY)
endproperty

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WRITE BURST

Sequence s;

(AWVALID && AWREADY)

Endsequence
Propert wr_burst(
@(posedgeACLK) AWVALID->|=>[*1:$] (BRESP==OKAY &&
BVALID && BREADY);
endproperty

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BURST TYPE checking

BURST_TYPE_CHECK:assert ( AWBURST<3 ||
ARBURST<3 ) else $warning ( This is reserved
burst type)

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BURST TYPE checking

BURST_TYPE_CHECK:assert ( AWBURST<3 ||
ARBURST<3 ) else $error ( This burst type is not
implemented)

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Cover property and cover group

assert: if you want scenario to be hold true then you write

an assertion.

cover : Whether scenario ever happened in your simulation

or not.

The difference is that covering a property ignores the

failures, and asserting a property ignores the passes.
Actually, you have a choice with an assert, You may want to
know that it passed at least once, and never fails.

An assertion that fails usually invalidates the entire test and

all associated coverage you have collected for that test.

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Sequence s
@(posedge clk) a ##1 b;

Endsequence
Propert p;
a->s;
Endproperty
Assert property(p);
Cover property(p)

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SLAVE RESPONSE

Property Rsp

( @(posedge ACLK) (RSESP==OAKY ||

BRESP==OKAY )
Endproperty
Assert_Rsp: assert property ( Rsp) $display( Normal
operation Completed) else $display ( Normal
operation is not completed)

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Property Rsp1( @(posedge ACLK) ( RRESP==1 ||

BRESP==1 )

Endproperty

Assert_Rsp: assert property ( Rsp)

$display( EXOKAY feature is completed
successfully ) else $display ( EXOKAY feature is
not completed successfully)

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Property Rsp1( @(posedge ACLK) ( RRESP==2 ||

BRESP==3)

Endproperty

Assert_Rsp: assert property ( Rsp) $display( Given

test is passed ) else $display ( Given test case
is failed due to slave error or decoder error )

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