Unit I

UNIT- I
INTRODUCTION TO PIC
MICROCONTROLLERS
MZCET/EEE/EE6008/1
1.1
Introduction to PIC Microcontroller
1.2
PIC 16C6x and PIC16C7x Architecture
1.3
PIC16cxx-Pipelining
1.4
Program Memory considerations
1.5
Register File Structure
1.6
Instruction Set
1.7
Addressing modes
1.8
Simple Operations.
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Introduction
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1.
1
Introduction
PIC -Peripheral Interface Controller

Brain child of Microchip Technology,
USA .
single chip micro-controllers
Industrial automation and embedded
applications
Low cost
Wide availability
Large user base
Extensive collection of application
notes
Availability of low cost or free
development tool
Serial programming capability
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1.
1
Introduction
Classification of PIC
microcontroller
Low-end
Mid-range devices
architectures
12-bit wide
instructions
with basic I/O
functions.
Upgradation of lowend architectures

with more number of
peripherals, more
number of registers.
An enhancement of
Analog to Digital
converter capability
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1
Introduction
Classification of PIC
microcontroller
Low-end
Mid-range devices
architectures
12C5XX
16C5X
16C505
16C6X
16C7X
16F87X
limited
More data/program
program
memory
Applicable in
memory
Applicable only
Medium range
in simple
projects.
interface
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6
functions.
1.
1
Introducti
Princeton on
Architecture
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1
Introducti
Harvard on
Architecture
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Series of PIC16C6X
PIC16C61
PIC16C62
PIC16C62A
PIC16CR62
PIC16C63
PIC16CR63
PIC16C64
PIC16C64A
PIC16CR64
PIC16C65
PIC16C65A
PIC16CR65
PIC16C66
PIC16C67
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Core features of
PIC16C6X
High performance RISC CPU
Only 35 single word instructions to

learn
All single cycle instructions except for
program branches which are two-cycle
Operating speed:
DC - 20 MHz clock input DC - 200 ns
instruction cycle
Interrupt capability
Eight level deep hardware stack
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2
Core features of
PIC16C6X
Direct, indirect,
and relative addressing
modes
Power-on Reset (POR)
Power-up Timer (PWRT) and Oscillator

Start-up Timer (OST)
Watchdog Timer (WDT) with its own onchip RC oscillator for reliable operation
Programmable code-protection
Power saving SLEEP mode
Selectable oscillator options
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1.
2
Peripheral features of
PIC16C6X
Timer0: 8-bit timer/counter with 8-bit

prescaler
Timer1: 16-bit timer/counter with
prescaler, can be incremented during
sleep via external crystal/clock
period register, prescaler and postscaler
Capture/Compare/PWM (CCP) module(s)
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2
Peripheral features of
PIC16C6X
Capture is 16-bit, max resolution is 12.5

ns, Compare is 16-bit, max resolution is
200 ns, PWM max resolution is 10-bit.
Synchronous Serial Port (SSP) with SPI
and I2C
Universal Synchronous Asynchronous
Receiver Transmitter (USART/SCI)
Parallel Slave Port (PSP) 8-bits wide,
with external RD, WR and CS controls
Brown-out detection circuitry for Brownout Reset (BOR)
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Pin Diagram of PIC16C6X
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1.
2
PinName
Pin out Description of

PinTypPIC16C61
Description
e
OSC1/CLKI I
N
O
OSC2/CLKO
UT
MCLR/VPP
I/P
RA0
RA1
RA2
I/O
I/O
I/O
Oscillatorcrystalinput/externalclock
sourceinput.
Oscillatorcrystaloutput.Connectsto
crystalor
resonator incrystal oscillatormode.
InRCmode,thepinoutputsCLKOUT
whichhas
1/4thefrequencyofOSC1,and
denotesthe
instructioncyclerate.
Masterclearresetinputorprogram
mingvoltage
input.Thispinisan
activelowresettothedevice.
PORTAisabi-directionalI/Oport.
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1.
2
Pinout Description of
PIC16C61
PinTy Description
PinNa
me
pe
RB0/INT
RB1
RB2
RB3
RB4
RB5
RB6
RB7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PORTBisabi-directionalI/Oport.
PORTBcanbesoftwareprogramme
dforinternalweakpulluponallinputs.
RB0canalsobetheexternalinterr
uptpin.
Interruptonchangepin.
Interruptonchangepin.Serialprogramm
ingclock.
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Serialprogrammingdata.
1.
2
PIC16C
62
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1.
2
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1.
2
PIC16C6
3
PIC16CR
63
PIC16C6
6
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1.
2
PIC16C62/62A/R62/63/R63
/66
PinName
PinTyp Description
e
OSC1/CLKIN I
O
OSC2/CLKO
UT
MCLR/VPP
I/P
RA0
RA1
I/O
I/O
Oscillatorcrystalinput/externalclocks
ourceinput.
Oscillatorcrystaloutput.Connectstocr
ystalor
InRCmode,thepinoutputsCLKOUTw
hichhas
denotesthe
Masterclearresetinputorprogrammin
gvoltage
input.Thispinisan
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1.
2
PIC16C62/62A/R62/63/R63
/66
PinNa PinTy Description
me
RB0/INT
RB1
RB2
RB3
RB4
RB5
RB6
RB7
pe
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
dforinternalweakpulluponallinputs.
uptpin.
ingclock.
21
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PIC16C62/62A/R62/63/R63/66
PinName
RC0/T1OSO(1)/T1CKI
RC1/T1OSI(1)/CCP2(2)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK(2)
RC7/RX/DT(2)
Pin Description
Type
I/O PORTC is a bi-directional I/O port.
RC0 can also be the Timer1 oscillator
output(1) or Timer1 clock input.
I/O RC1 can also be the Timer1 oscillator
input(1) or Capture2 input/Compare2
output/PWM2 output(2).
I/O RC2 can also be the Capture1
input/Compare1 output/PWM1 output.
I/O RC3 can also be the synchronous
serial clock input/output for both SPI
and I2C modes
I/O RC4 can also be the SPI Data In (SPI
mode) or data I/O (I2C mode).
I/O RC5 can also be the SPI Data Out (SPI
mode).
I/O RC6 can also be the USART
Asynchronous Transmit(2) or
Synchronous Clock(2).
22
I/O RC7 can alsoMZCET/EEE/EE6008/1
be the USART
1.
2
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2
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2
PIC16C65A
PIC16CR65
PIC16C67
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1.
2
PIC16C64/64A/65/65A/67
PinName
PinTyp Description
e
OSC1/CLKIN I
ourceinput.
O
ystalor
OSC2/CLKO
UT
hichhas
denotesthe
MCLR/VPP
I/P
gvoltage
input.Thispinisan
RA0
I/O
26
RA1
I/O
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PIC16C64/64A/65/65A/67

me
pe
dforinternalweakpullRB0/INT I/O
uponallinputs.
RB1
I/O
RB2
I/O
uptpin.
RB3
I/O
RB4
I/O
RB5
I/O
RB6
I/O
RB7
I/O
ingclock.
27
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PIC16C64/64A/65/65A/67
PinName
RC0/T1OSO(1)/T1CKI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK(2)
Pin Description
Type
input/Compare1 output/
PWM1 output.
and I2C modes
mode) or data I/O (I 2C mode).
mode).
28
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2
PIC16C64/64A/65/65A/67
PinName PinTyp
e
RD0/PSP I/O
0
I/O
RD1/PSP I/O
1
I/O
RD2/PSP I/O
2
I/O
RD3/PSP I/O
3
I/O
RD4/PSP
4
RD5/PSP
5
RD6/PSP
6
RD7/PSP
7
Description
PORTD can be a bi-directional I/O port or
parallel slave port for interfacing to a
microprocessor bus.
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PIC16C6X Device varieties
C, as in
PIC16C64-
EPROM type memory

and operate over the
standard voltage range
LC, as in
PIC16LC64
EPROM type memory

and operate over an
extended voltage range
CR, as in
PIC16CR64
ROM program memory

and operate over the
standard voltage range
LCR, as in
PIC16LCR64
ROM program memory

and operate over an
extended voltage range
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PIC16C6X Device varieties
UV Erasable Devices
The UV erasable version, offered in CERDIP

package is optimal for prototype development and
pilot programs.
This version can be erased and reprogrammed to
any of the oscillator modes.
ne-Time-Programmable
(OTP) Devices
Flexibility for frequent code updates and small
volume applications.
Packaged in plastic packages, permit the user to
program them once.
In addition to the program memory, the

configuration bits must also be programmed.
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PIC16C6X DEVICE VARIETIES
ck-Turnaround-Production (QTP) Devices

Available for users who choose not to program a
medium to high quantity of units
whose code patterns have stabilized.
Identical to the OTP devices but with all EPROM
locations and configuration options already
programmed by the factory.
Read Only Memory (ROM) Devices

Masked ROM versions of several of the highest
volume parts
Low cost option for high volume, mature products.
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PIC16C6X DEVICE VARIETIES
Serialized
Quick-Turnaround
Production (SQTPSM) Devices
A unique programming service where a few userdefined locations in each device are programmed
with different serial numbers.
The serial numbers may be random, pseudorandom, or sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password, or ID number.
ROM devices do not allow serialization information
in the program memory space.
The user may have this information programmed in
the data memory space.
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Architecture
of PIC16C61
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PIC16C62/62A/R62/64/64A/R64
BLOCK
35
1.
2
PIC16C62/62A/R62/64/64A/
R64 BLOCK DIAGRAM
1: Higher order bits are from the STATUS register.

2: PORTD, PORTE and the Parallel Slave Port are not
available on the PIC16C62/62A/R62.
3: Brown-out Reset is not available on the
PIC16C62/64.
4: Pin functions T1OSI and T1OSO are swapped on
the PIC16C62/64.
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PIC16C63/R63/65/65A/R65
DIAGR
PIC16C63/R63/65/65A/R65 BLOCK 37
1.
2
PIC16C63/R63/65/65A/R65 BLOCK DIAGRA

2: PORTD, PORTE and the Parallel Slave Port are
not available on the PIC16C63/R63.
PIC16C65.
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1.
2
MZCET/EEE/EE6008/1PIC16C66/67
39
BLOCK DIAGRAM
1.
2
PIC16C66/67 BLOCK DIAGRAM

1: Higher order bits are from the
STATUS register.
2: PORTD, PORTE and the Parallel Slave
Port are not available on the PIC16C66.
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1.
2
Architectural overview
RISC microprocessors.
Harvard architecture, in which, program and
data are accessed from separate memories
using separate buses.
This improves bandwidth over traditional von
Neumann architecture.
Separating program and data busses further
allows instructions to be sized differently than
8-bit wide data words.
Instruction opcodes are 14-bits wide making it
possible to have all single word instructions.
A 14-bit wide program memory access bus
fetches a 14-bit instruction in a single cycle.
All instructions execute in a single cycle (200
ns @ 20 MHz) except for program branches.
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1.
2
The PIC16CXX device contains an 8-bit ALU

and working register (W).
Arithmetic and logic

unit
It performs arithmetic and Boolean
functions between data in the working
register and any register file.
The ALU is 8-bits wide and capable of
addition, subtraction, shift, and logical
operations.
Arithmetic operations are two's complement
in nature.
Depending upon the instruction executed,
the ALU may affect the values of the Carry
(C), Digit Carry (DC), and Zero (Z) bits in the
42
STATUS register. MZCET/EEE/EE6008/1
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Working register (W register)

The W register is an 8-bit working register
used for ALU operations.
It is not an addressable register.
In two-operand instructions, typically one
operand is the working register (W register),
the other operand is a file register or an
immediate constant.
In single operand instructions, the operand
is either the W register or a file register.
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1.
2
Comparison of 16C6X
series
PIC16C PIC16C PIC16C PIC16C PIC16C
61
62A
R62
63
R63
Clock
Maximu
m
Frequen
cy
of
Operatio
n (MHz)
20
20
20
20
20
Memor
y
EPROM
Program
Memory
(x14
words)
1K
2K
4K
ROM
Program
Memory
(x14
words)
2K
4K
Data
Memory
36
128
128
192
192
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1.
2
Comparison of 16C6X
series
PIC16C6 PIC16C6 PIC16C6 PIC16C6
4A
5A
Clock
Maximum
Frequenc
y
of
Operation
(MHz)
20
20
20
20
Memory
EPROM
Program
Memory
(x14
words)
2K
4K
8K
8K
ROM
Program
Memory
(x14
words)
Data
Memory
(bytes)
128
192
368
368
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1.
2
Comparison of 16C6X
series
61
Periphe Timer
rals
Module(
s)
TMR0
62A
R62
63
R63
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
Capture/
Compar
e/
PWM
Module(
s)
Serial
Port(s)
(SPI/I2C,
USART)
SPI/I2C
SPI/I2C
SPI/I2C
USART
SPI/I2C
USART
Parallel
Slave
Port
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1.
2
Comparison of 16C6X
series
PIC16C6
4A
Peripher
als
PIC16C6
5A
PIC16C6
6
PIC16C6
7
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
Serial
Port(s)
(SPI/I2C,
USART)
SPI/I2C
SPI/I2C
USART
SPI/I2C
USART
SPI/I2C
USART
Parallel
Slave
Port
Yes
Yes
Yes
Yes
Timer
TMR0,
Module(s) TMR1,
TMR2
Capture/C
ompare/
PWM
Module(s)
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1.
2
Comparison of 16C6X
series
PIC16C PIC16C6 PIC16CR6 PIC16C
61
Feature
s
Interrupt
Sources
2A
63
PIC16CR
63
10
10
I/O Pins
13
22
22
22
22
Voltage
Range
(Volts)
3.0-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
InCircuit
Serial
Program
ming
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Brownout
Reset
Package
s
18-pin 28-pin
DIP, SO SDIP,
28-pin
SDIP,
SOIC,
SOIC,
SSOP
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SSOP
28-pin
SDIP,
SOIC
28-pin
SDIP,
SOIC
48
1.
2
Comparison of 16C6X
series
PIC16C6 PIC16C65 PIC16C66
PIC16C6
4A
Features
Interrupt
Sources
A
8
11
10
11
I/O Pins
33
33
22
33
Voltage
Range
(Volts)
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
In-Circuit
Serial
Programm
ing
Yes
Yes
Yes
Yes
Brown-out
Reset
Yes
Yes
Yes
Yes
Packages
40-pin
40-pin
DIP;
DIP;
44-pin
44-pin
PLCC,
PLCC,
MQFP,
MQFP,
TQFPMZCET/EEE/EE6008/1
TQFP
28-pin
SDIP,
SOIC,
SSOP
40-pin
DIP;
44-pin
PLCC,
MQFP,
TQFP
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1.
2
PIC16C7
X
PIC16C7
2
PIC16C7
3
PIC 16C7X
series
PIC16C7
3A
PIC16C7
4
PIC16C7
4A
PIC16C7
6
PIC16C7
7
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1.
2
PIC16C7X Core Features:
High-performance RISC CPU

Only 35 single word instructions to learn
All single cycle instructions except for program
branches which are two cycle
Operating speed: DC - 20 MHz clock input DC 200 ns instruction cycle
Up to 8K x 14 words of Program Memory, up to
368 x 8 bytes of Data Memory (RAM)
Interrupt capability
Eight level deep hardware stack
Direct, indirect, and relative addressing modes
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1.
2
PIC16C7X Core Features:
Power-on Reset (POR)

Power-up Timer (PWRT) and Oscillator Startup Timer (OST)
Watchdog Timer (WDT) with its own on-chip
RC oscillator for reliable operation
Programmable code-protection
Power saving SLEEP mode
Selectable oscillator options
Low-power, high-speed CMOS EPROM
technology
Fully static design
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PIC16C7X Peripheral Features:

prescaler
Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via external
crystal/clock
Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
Capture, Compare, PWM module(s)
Capture is 16-bit, max. resolution is 12.5 ns
Compare is 16-bit, max. resolution is 200 ns
PWM max. resolution is 10-bit
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2
PIC16C7X Peripheral Features:

8-bit multichannel analog-to-digital converter
Synchronous Serial Port (SSP) with SPI
Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
Parallel Slave Port (PSP) 8-bits wide, with
external RD, WR and CS controls
Brown-out detection circuitry
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1.
2
PIC16C72
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1.
2
PIC16C73
PIC16C76
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1.
2
PIC16C74
PIC16C77
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1.
2
PinName

PinTypPIC16C72/73/76
Description
e
OSC1/CLKIN I
O
OSC2/CLKO
UT
MCLR/VPP
I/P
RA0/AN0
RA1/AN1
RA2/AN2
I/O
I/O
I/O
ourceinput.
ystalor
hichhas
denotesthe
gvoltage
input.Thispinisan
Can also be analog input 0
Can also be analog input 1
58
Can also be analog
input 2
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2

PIC16C72/73/76

me
pe
dforinternalweakpullRB0/INT I/O
uponallinputs.
RB1
I/O
RB2
I/O
uptpin.
RB3
I/O
RB4
I/O
RB5
I/O
RB6
I/O
RB7
I/O
ingclock.
59
Serialprogrammingdata.
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PinName

PIC16C72/73/76
Pin Description
Type
RC0/T1OSO(1)/T1CKI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK(2)
RC7/RX/DT(2)

input/Compare1 output/
PWM1 output.
and I2C modes
mode) or data I/O (I 2C mode).
mode).
60
I/O RC7 can alsoMZCET/EEE/EE6008/1
be the USART
1.
2
PIC16C74/77
(additional
apart from 72/73/76)
PinName PinTyp
Description
e
RD0/PSP0 I/O
PORTD can be a bi-directional I/O port or
RD1/PSP1 I/O
parallel slave port for interfacing to a
RD2/PSP2 I/O
microprocessor bus.
RD3/PSP3 I/O
RD4/PSP4 I/O
RD5/PSP5 I/O
RD6/PSP6 I/O
RD7/PSP7 I/O
PORTE is a bi-directional I/O port.
RE0/RD/A I/O
RE0 can also be read control for the
N5
parallel slave port OR analog Input 5
I/O
RE1 can also be write control for the
RE1/WR/A
parallel slave port. Or
N6
I/O
Analog input 6
RE2 can also be select control for the
RE2/CS/A
parallel slave port or Analog input7
61
N7
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2
PIC16C72 BLOCK DIAGRAM
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1.
2
PIC16C73/73A/76
BLOCK DIAGRAM
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1.
2
PIC16C73/73A/76
DIAGRAM
BLOCK
Device
Program
Memory
Data
Memory
(RAM)
PIC16C73
4K x 14
192 x 8
PIC16C73A
4K x 14
192 x 8
PIC16C76
8K x 14
368 x 8
Note
PIC16C73.
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1.
2
MZCET/EEE/EE6008/1
PIC16C74/74A/77
BLOCK DIAGRAM
65
1.
2
PIC16C74/74A/77
DIAGRAM
BLOCK
Device
Program
Memory
Data
Memory
(RAM)
PIC16C74
4K x 14
192 x 8
PIC16C74A
4K x 14
192 x 8
PIC16C77
8K x 14
368 x 8
Note
PIC16C74.
MZCET/EEE/EE6008/1
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1.
2
RISC microprocessors.
Harvard architecture
Improves bandwidth over traditional von
Neumann architecture
Separating program and data buses allows
instructions to be sized differently than the
8-bit wide data word.
Instruction opcodes are 14-bits wide
A 14-bit wide program memory access bus
fetches a 14-bit instruction in a single cycle.
MZCET/EEE/EE6008/1
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1.
2
A twostage pipeline overlaps fetch and

execution of instructions
All instructions (35) execute in a single cycle
(200 ns @ 20 MHz) except for program
branches.
Directly or indirectly address its register files or
data memory.
All special function registers, including the
program counter, are mapped in the data
memory.
Orthogonal (symmetrical) instruction set.
Lack of special optimal situations make
efficient programming
MZCET/EEE/EE6008/1
68
1.
2
CPU Registers
Working Register (W)

Status Register
FSR File Select Register
INDF
PCLATH
Program Counter
PCL
Eight Level Stack
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1.
2
Comparison of 16C7X
series
PIC16C PIC16C
72
73
PIC16C
74
PIC16C
76
PIC16C
77
Clock
Maximu
m
Frequen
cy
of
Operatio
n (MHz)
20
20
20
20
20
Memor
y
EPROM
Program
Memory
(x14
words)
2K
4K
4K
8K
8K
Data
Memory
(bytes)
128
192
192
368
368
MZCET/EEE/EE6008/1
70
1.
2
Comparison of 16C7X
series
Periphe Timer
rals
Module(
s)
72
73
74
76
77
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
Capture/
Compar
e/
PWM
Module(
s)
Serial
Port(s)
(SPI/I2C,
USART)
SPI/I2C
SPI/I2C
USART
SPI/I2C
USART
SPI/I2C
USART
SPI/I2C
USART
Parallel
Slave
Port
Yes
Yes
A/D
MZCET/EEE/EE6008/1
5
71
1.
2
Comparison of 16C7X
series
PIC16C PIC16C7 PIC16C74 PIC16C PIC16C
72
Feature
s
Interrupt
Sources
3
8
11
12
76
77
11
12
I/O Pins
22
22
33
22
33
Voltage
Range
(Volts)
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
InCircuit
Serial
Program
ming
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Brownout
Reset
Package
s
28-pin
SDIP,
SOIC,
SSOP
28-pin
40-pin
SDIP,
SDIP,
SOIC,
PLCC,
SSOP
MZCET/EEE/EE6008/1
MQFP,
28-pin
SDIP,
SOIC
40-pin
SDIP,
PLCC,
72
MQFP,
1.
3
Pipelining
MZCET/EEE/EE6008/1
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1.
3
Pipelining
MZCET/EEE/EE6008/1
74
1.
3
Pipelining
Clocking Scheme/Instruction Cycle
Internal division of oscillator clock input as Q1,

Q2, Q3, and Q4.
PC is incremented every Q1
Instruction is fetched from the program memory
Latched into the instruction register in Q4.
Decoding and execution in next Q1 through Q4.
MZCET/EEE/EE6008/1
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1.
3
Pipelining
Cyc
le
Fetch of
nth
instructi
on from
address
n
Cyc
le
Executio
n
of nth
instructi
on
Fetch of
(n+1)th
instruction
from
address
n+1
(goto New
address
Instruction)
Cyc
le
Cyc
le
Change
program
counter
to new
address
Fetch of
(n+2)th
instruction
from
address n+2
MZCET/EEE/EE6008/1
Ignore the
(n+2)th
instruction
Fetch
instruction
from new
address
76
1.
3
Pipelining
An Instruction Cycle consists of four Q cycles

(Q1, Q2, Q3, and Q4).
The instruction fetch and execute are pipelined
Fetch takes one instruction cycle
Decode and execute takes another instruction
cycle.
Due to the pipelining, each instruction
effectively executes in one cycle.
MZCET/EEE/EE6008/1
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1.
3
Pipelining
Two cycle
instruction(Branch)
A fetch cycle begins with the program counter
(PC) incrementing in Q1.
In the execution cycle, the fetched instruction
is latched into the Instruction Register (IR) in
cycle Q1.
This instruction is then decoded and executed
during the Q2, Q3, and Q4 cycles.
Data memory is read during Q2 (operand read)
and written during Q4 (destination write).
MZCET/EEE/EE6008/1
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1.
3
Pipelining (Example)
CY
1
CY
2
Fetc
h1
loop
CY
3
Execut
e1
Fetch 2 Execut
e2
Fetch3
Address Instruction
1
MOVLW 55h
MOVWF
PORTB
CALL SUB-1
CY
4
Execut
e3
Fetch4
CY
5
CY
6
Flush
Fetch
SUB-1
Execute
SUB-1
BSF PORTA,
All instructions
BIT3 are single cycle, except for any
branches.
These take two cycles since the
SUB-program
5
ADDW
fetch instruction is flushed from the pipeline while
1
the new instruction MZCET/EEE/EE6008/1
is being fetched and then
executed.
79
1.
4
Memory organisation
It has three memory blocks.

Program memory
Data memory
Stack
MZCET/EEE/EE6008/1
80
1.
4
Program memory Considerations
How to access 2K Program

memory counter
Program
(13 bit)
1
2
11 10
X X 0 1 1 1 1 1 0 0 1 1
Ignored
Bits
Hex
address
000
Program
memory
7
2K
Addresses
(11 bit
range)
.
.
3E7
.
.
.
MZCET/EEE/EE6008/1
.
7FF
81
1.
4
How to access 4K Program

memory counter
Program
(13 bit)
1
2
11
X 1 0 1 1 1 0 1 0 0 1 0
Ignored
Bit
Hex
address
000
Program
memory
5
4K
Addresses
(12 bit
range)
.
.
BA5
.
.
.
MZCET/EEE/EE6008/1
.
FFF
82
1.
4
Each PIC 16CXX family either consists of 2K or 4K

addresses of program memory
A program memory of 2K needs only an 11 bit
program counter to access any address.
A program memory of 4K needs only an 12 bit
program counter to access any address.
13 bit program counter allowing extension of
PROM into 8K program memory without changing
the CPU structure.
For the 4K and 2K parts the upper bits are similarly
ingored during fetches
from program memory.
MZCET/EEE/EE6008/1
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1.
4
Structure of Mainline program

Mainline
Call Initial
; Initialize everything
Mainloop
Call Task1
; Deal with Task1
Call Task2
; Deal with Task2,
.
.
.
.
Call Looptime ;Force looptime to a fixed
value
goto mainloop ;Repeat
MZCET/EEE/EE6008/1
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1.
4
Program Memory
Map
Hex address
0
00
001
Goto main
line
Program
memory
002
003
004
005
Goto
Intservice
Tables
End of
Tables
Mainline
IntService
MZCET/EEE/EE6008/1
FFF
Mainline
program
and its
subroutine
s
Interrupt
service
routine
and its
subroutine
85
s
1.
4
Two addresses are treated in a special way

by the CPU.
After reset state, its program counter is at
zero.
Content of address H0001 being goto
Mainline instruction.
when an interrupt occurs, second special
address H004, is loaded into the PC.
A goto Intservice instruction
assigned to this address
can
be
86
Cause the CPU toMZCET/EEE/EE6008/1
jump to the beginning of
1.
4
If task 1 is supposed to toggle an LED

indicator lamp every half second, then it
need only increment a scale of 50 counter
once per call of Task1.
Then LED will be toggled once for each
complete cycle of this counter.
The mainline program begins execution
when PIC comes out of resent.
It continues running until one of the PICs
interrupt sources request service.
At that point, the execution of mainline code
is temporarily suspended.
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1.
4
CPU begins the execution of the

interrupt
service
routine
by
automaticaaly loading the program
counter with H004.
At the completion of interrupt service
routine, CPU returns to where it left off
in the Mainline program.
Program writing is somewhat simplified
if all the program code for the tables,
the
mainline
program
and
its
subroutines, interrupt service routine
and its subroutines take up less than
MZCET/EEE/EE6008/1
88
1.
4

Program
memory
Hex
address
How 11 bit call instruction is

executed
X X
4
1
2
000
.
.
PC LATH
PC
LATH,3 =
0
0
11
.
.
7FF
2K
Addresses
(11 bit
range)
4K
Addresses
(12 bit
range)
800
0
Program counter
(13 bit)
.
PC
LATH,3 =
1
MZCET/EEE/EE6008/1
.
FFF
.
89
1.
4
It is a result of having a one word subroutine

call instruction.
Bits of 10.0 of the call instruction are loaded
into the program counter.
At the same time, bits 4 and 3 of a special
register called PCLATH ( program counter
Latch) are loaded into bits 12 and 11 of the
program counter.
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1.
4
As long as the program memory is less than

2048 words, bits 4 and 3 of PCLATH can be
left initialized to H00,.
11 address bits in the call instruction will
identify the starting address of any subroutine
located upto address F7FF.
Programs larger than this, it is necessary to
ensure that bit 3 of PCLATH is set or cleared
appropriately each time a subroutine is called.
The Goto instruction which also has an 11 bit
address field requires an same treatment.
MZCET/EEE/EE6008/1
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1.
5
Data memory
ata Memory is also known as Register File.
Register File consists of two

components.
General purpose register file ( RAM).
Special purpose register file (similar
to SFR in 8051).
MZCET/EEE/EE6008/1
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1.
5
0
0
8
0
Special
Purpose
Registers
(32 bytes)
1
F
2
9
F
A
Special
Purpose
Registers
(32 bytes)
RAM
(32 bytes)
RAM
(96 bytes)
7
F
Bank 0
(128 bytes)
F
F
Extra RAM
(64 bytes)
In
PIC16C63
PIC16C65A
PIC16C73A
PIC16C74A
Bank 1
(128 bytes)
93
MZCET/EEE/EE6008/1
1.
5
Typical SFRs
GPR
General Purpose Registers STATUS
OPTION
User program data
PCLATH
PCL
Statusword+flags
Timeroptions
Componentsofpro
gram
counter(PC)
FileSelectforindir
SFR
FSR
ectdata
addressing
Special Function Registers
INTCON,PIR1, Componentsofinte
Reserved for
Control / configuration
Peripheral access
Indirect addressing
Program counter
Core SFRs
Appear in every bank at
MZCET/EEE/EE6008/1
same file address
PIE1,
PIR2,PIE2
rrupt
handling
PORTA,TRISA,
Accesstoparallelp
orts
TMR0,OPTION
,
INTCON,
Timer0
TXREG,TXSTA,
Accesstoserialpor
RCREG,RCSTA t
,
94
ADRESH,ADRE
1.
5
The register file can be

accessed
either directly, or
indirectly,
through
the
File
Select Register (FSR)
MZCET/EEE/EE6008/1
95
1.
5
SPECIAL FUNCTION REGISTERS
TATUS REGISTER (ADDRESS 03h, 83h)
bit 7 IRP(1): Register Bank Select bit (used for indirect

addressing)
1 = Bank 2, 3 (100h - 1FFh) ;
0 = Bank 0, 1 (00h - FFh)
bit 6-5 RP1(1):RP0: Register Bank Select bits (used for direct
addressing)
11 = Bank 3 (180h - 1FFh) ;
10 = Bank 2 (100h - 17Fh) ;
01 = Bank 1 (80h - FFh) ;
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
MZCET/EEE/EE6008/1
96
0 = A WDT time-out occurred
1.
5
TATUS REGISTER (ADDRESS 03h, 83h)

bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction ;
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/ borrow bit (ADDWF,ADDLW,SUBLW,SUBWF
instructions)
(for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C(2): Carry/ borrow bit (ADDWF,ADDLW,SUBLW,SUBWF
instructions)
1 = A carry-out from the most significant bit of the result
occurred
0 = No carry-out from the
most significant bit of the result
MZCET/EEE/EE6008/1
occurred
97
1.
5
Special Purpose Registers
The special purpose register file consists of

input/output ports and control registers.
Addressing from 00H to FFH requires 8 bits of
address.
Instructions that use direct addressing modes in
PIC to address these register files use 7 bits of
instruction only.
Register bank select (RP0) bit in the STATUS
register is used to select one of the register bank
MZCET/EEE/EE6008/1
98
1.
5
INDFRegister
NDF
Core SFR accessible at file address 00h in all banks
Virtual pointer not physical register In register file,
Tracks contents of FSR
Simplifies pointer arithmetic
[05] =
10h
[06] =
0Ah
xample
In register file,
Load FSR 05
[INDF] = 10h
[05]
= FSR
10h 05
Load
FSR
; points to file address 05
[06]
= 0Ah
[INDF]
= 10h
FSR++
FSR++
INDF
points to file address 05
;
= 06
0Ah
increment FSR [INDF]
FSR =
;
points to file address 06

[INDF] = 0Ah INDF
;
MZCET/EEE/EE6008/1
99
1.
5
PTION Register (ADDRESS 81h)
The OPTION_REG register is a readable and

writable register, which contains various control bits
to configure the TMR0/WDT prescaler, the external
INT Interrupt, TMR0 and the weak pull-ups on PORTB.
bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port
latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
MZCET/EEE/EE6008/1
100
1.
5
OPTION Register (ADDRESS 81h)
bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on
RA4/T0CKI pin
0 = Increment on low-to-high transition on
RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
MZCET/EEE/EE6008/1
101
1.
5
OPTION Register (ADDRESS 81h)
bit 2-0 PS2:PS0:

Prescaler Rate Select bits
Bit value
TMR0
Rate
WDT Rate
000
1:2
1:1
001
1:4
1:2
010
1:8
1:4
011
1:16
1:8
100
1:32
1:16
101
1:64
1:32
110
1:128
1:64
111
1:256
1:128
MZCET/EEE/EE6008/1
102
1.
5
NTCON Register (ADDRESS 0Bh, 8Bh)
bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts ;
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts;
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt;
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt;
0 = Disables the RB0/INT external interrupt
MZCET/EEE/EE6008/1
103
1.
5
TCON Register (ADDRESS 0Bh, 8Bh)
bit 3 RBIE: RB Port Change Interrupt Enable

bit
1 = Enables the RB port change interrupt;
0 = Disables the RB port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared
in software)
0 = TMR0 register did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the
RB7:RB4 pins changed
MZCET/EEE/EE6008/1
state(1)
104
1.
5

PIE1 Register (ADDRESS 8Ch)
bit 7 PSPIE(1): Parallel Slave Port Read/Write Interrupt

Enable bit
1 = Enables the PSP read/write interrupt;
0 = Disables the PSP read/write interrupt
bit 6 ADIE(2): A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt;
0 = Disables the A/D interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt;
0 = Disables the USART receive interrupt
MZCET/EEE/EE6008/1
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1.
5

PIE1 Register (ADDRESS 8Ch)
bit 4 TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt;
0 = Disables the USART transmit interrupt
bit 3 SSPIE: Synchronous Serial Port Interrupt
Enable bit
1 = Enables the SSP interrupt;
0 = Disables the SSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt;
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt
Enable bit
1 = Enables the TMR2 to PR2 match interrupt;
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
MZCET/EEE/EE6008/1
106
1 = Enables the TMR1
overflow interrupt;
1.
5
PCON REGISTER
(ADDRESS 8Eh)
R = Readable bit
W = Writable bit
U ='0'
Unimplemented bit,
bit 7-2: Unimplemented: Read as
read as
bit 1: POR: Power-on Reset Status 0
bit
1 = No Power-on Reset occurred- n = Value at POR reset
0 = A Power-on Reset occurred q = value depends on
conditions
(must be set in software after a Power-on Reset

occurs)
bit 0: BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred
(must be set in software after a Brown-out Reset
MZCET/EEE/EE6008/1
occurs)
107
1.
5
CPU Registers
Program Counter
PC low (PCL) = PC<7:0>

Accessible by instruction reads/writes
PC high (PCH) = PC<12:8>

Not directly accessible to instructions
PC latch high (PCLATH)

Core SFR accessible at file address 0Ah in all
page
offset
banks
PCL
PCH
PCH
= PC<12:8> = PCLATH<4:0> 3
PC 12 11 10 9 8 7 6 5 4
PCLATH<7:5> not implemented
4
0 PCLATH
MZCET/EEE/EE6008/1
108
1.
5
PCL and PCLATH
CPU Registers
The program counter (PC)
is 13-bits wide.
The low byte comes from
the PCL register, which is
a readable and writable
register.
The
upper
bits
(PC<12:8>)
are
not
readable,
but
are
indirectly
writable
through
the
PCLATH
register.
On any RESET, the upper
bits of the PC will be
cleared
The upper one how the
PC is loaded on a write to
PCL
(PCLATH<4:0>
MZCET/EEE/EE6008/1
109
PCH).
1.
5
InstructionMemoryS
pace
All8bitMCUs
Instruction address
n bit location address
Location = instruction
2n instructions
Instruction width
instruction 11 111
Page2 instruction 11 000
instruction 01 111
12 / 14 / 16 bits
instruction 01 011
Page
instruction 01 010
Partition of instruction
instruction 01 001
instruction 01 000
memory space
instruction 00 111
2k instructions / page
k bit offset
Page 1instruction 00 011
instruction 00 010
n bitaddress
instruction 00 001
instruction 00 000
n k bits
k bits
page offset
offset
page
Memory
MZCET/EEE/EE6008/1
Location Address 110
1.
5
InstructionMemoryS
pace
All8bitMCUs
Mid-Range instruction
memory
14-bit instruction word
13 bitPC
11 bits
2 bits
page
n = 13
12
11
k = 11
2 = 819211instruction words
Page
= 2 = 2048 = 800h words
10
offset
13
Program counter (PC)

PC<12:11> = page number 4 pages
PC<10:0> = offset
Reserved addresses
Address 0h
MZCET/EEE/EE6008/1
Reset vector pointer
to reset routine
111
1.
5
Call/Return
Stack
8 level FILO buffer
Holds 13 bit instruction addresses on CALL/RETURN
literal
CALL
STACK
PC
RETURN
10
12
11
10
PCLATH
Function entry
CALL instruction
STACK PC<12:0>
PCL literal<10:0> from instruction
PCH<12:11> PCLATH<4:3>
Function exit
RETURN instruction
PC<12:0> STACK
PCLATH not updated
MZCET/EEE/EE6008/1
May be different from
PCH after RETURN
112
InstructionFo
rmat
7
6
0
1.
6
13
opcode
13
10
7 6
opcode
Byte
d = oriented
0 destination = W
d = 1 destination = f
f = 7 bit file address
Bit oriented
b = bit position in register
f = 7 bit file address

13
opcode
13
11
opcode
General
literal
k = 8 bit literal (immediate)
CALL /
GOTO
k = 11 bit literal (immediate)
10
k
MZCET/EEE/EE6008/1
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1.
6
Mnemoni
c
InstructionS
et
Single bit
Manipulation
Operan
ds
Description
Cycl
es
bcf
f,b
Clear bit b of register 1

f,
Where bit b = 0 to 7
bsf
f,b
set bit b of register f, 1

Where bit b = 0 to 7
MZCET/EEE/EE6008/1
Status
bits
affected
114
1.
6
InstructionS
et
Clear/move
Mnemoni
c
Operan
ds
clrw
Description
Cycl
es
Status
bits
affected
Clear W
Z
Z
clrf
movlw
f
k
Clear f
Move literal value to
W
1
1
movwf
Move the value of W

to f
movf
f,F(W) Move the value of f

to F or W
swapf
f,F(W) Swap nibbles of f,

putting
result into F
MZCET/EEE/EE6008/1
115
1.
6
InstructionS
et
Increment/Decrement/comple
ment
Mnemoni
c
Operan
ds
incf
Description
Cycl
es
Status
bits
affected
f,F(W) Increment f, putting

result into F or W
decf
f,F(W) Decrement f, putting

result into F or W
comf
f,F(W) Complement f,
putting result into F
or W
MZCET/EEE/EE6008/1
116
1.
6
InstructionS
et
Addition/Subtractio
n
Mnemoni
c
Operan
ds
addlw
Description
Cycl
es
Status
bits
affected
C, DC,
Z
addwf
f,F(W) Add W with f, Putting 1

result into F or W
C, DC,
Z
sublw
Subtract W from
literal value, putting
result in W
C, DC,
Z
subwf
f,F(W) Subtract W from f,

putting result in F or
W
C, DC,
Z
Add literal value into

W
MZCET/EEE/EE6008/1
117
1.
6
InstructionS
et
Multiple bit
Mnemoni
c
manipulation
Operan
Description
Cycle
s
Status
bits
affected
andlw
AND literal value into

W
andwf
f,F(W)
AND W with f, Putting

result into F or W
iorlw
Inclusive OR literal
value into W
iorwf
f,F(W)
Inclusive OR W with f, 1
Putting result into F or
W
xorlw
Exclusive OR literal
value into W
ds
MZCET/EEE/EE6008/1
118
1.
6
InstructionS
et
Rotate
Mnemoni
c
Operan
ds
rlf
rrf
Description
Cycl
es
Status
bits
affected
f,F(W) Copy f into F or W;

Rotate F or W left
through the carry bit
f,F(W) Copy f into F or W;

Rotate F or W right
through the carry bit
MZCET/EEE/EE6008/1
119
1.
6
InstructionS
et
Conditional Branch
Mnemoni
c
Operan
ds
Description
Cycl
es
btfsc
f,b
Test bit b of register

f, where bit b = 0 to
7;
Skip if clear.
1
(2)
btfss
f,b
Test bit b of register

f, where bit b = 0 to
7;
Skip if set.
1
(2)
decfsz
f,F(W) Decrement f, putting

result into F or W;
Skip if zero.
1
(2)
incfsz
MZCET/EEE/EE6008/1
f,F(W) increment
f, putting
Status
bits
affected
120
1.
6
InstructionS
et
unconditional
Mnemoni
c
Branch Description
Operan
ds
Cycl
es
goto
Label
Go to labeled
instruction
call
label
Call labeled
instruction
Return from
subroutine
Return from
subroutine, putting
literal value in W
return
retlw
retfie
Return
from interrupt 2
MZCET/EEE/EE6008/1
Status
bits
affected
121
1.
6
InstructionS
et
Miscellaneous
Mnemoni
c
Operan
ds
Description
Cycl
es
Status
bits
affected
clrwdt
Clear watch dog

timer
NOT_T
0,
NOT_P
D
sleep
Go to in standby
mode
NOT_T
0,
NOT_P
D
nop
No operation
MZCET/EEE/EE6008/1
122
1.
7
AddressingModes
Direct
Addressing
7
X
RP
1
RP
0
STATUS Register
Bank
Address
00
Content
MZCET/EEE/EE6008/1
Instruct
ion
80
Bank
0
7F
Bank
1
FF
123
1.
7
AddressingModes
REG<b>
REG<a:b>
Notation
Bitb inregisterREG
Bitsa tob
inregisterREG
ConcatenationofA
andB
A.B
(A bitsfollowedbyB
Direct addressing
RP1
bits)
Program specifies data address
Bank selection
STATUS bits RP1 and RP0

On reset
RP1 = RP0 = 0 bank 0
selected
Bank switching
Write to STATUS<6:5>
RP0
7bitsfrominstruction
bank
8
6
7 5
fileaddress
4
0
1
File Address
Literal field in instructionMZCET/EEE/EE6008/1
124
1.
7
AddressingModes
Indirect Addressing
7
IRP
1
STATUS Register
FSR
1
Bank
Address
00
IND
F
MZCET/EEE/EE6008/1
80
Bank
0
7F
Bank
1
FF
125
1.
7
AddressingModes
Indirect addressing
Program writes to Special Function Registers (SFRs)
Address formed from SFRs
Instructions can increment/decrement SFR values

Similar to pointer arithmetic
File Select Register (FSR)

Core SFR accessible at file address 08h in all banks
File Address
IRP
FSR<6:0>
8bitsofFSR
bank
Bank
fileaddress
6
IRP.FSR<7>
STATUS bit IRP (Indirect Register Pointer)
1
4
On small devices
1 or 2 banks = 128 or 256 bytes of data memory
8 bit FSR address covers 2 banks
IRP not implemented (read 0 / write = NOP)
MZCET/EEE/EE6008/1
126
1.
8
SampleProgra
m
In register file,
RAMInitialization
[05] =
CLRF STATUS ; STATUS 0
MOVLW 0x20 ; W 1st address in GPR bank10h
0
[06] =
MOVWF FSR ; Indirect address register W
0Ah
Bank0_LP
Load FSR
CLRF INDF0 ; address in GPR 0
05
INCF FSR
; FSR++ (next GPR address)
BTFSS FSR, 7
; skip if (FSR<7> == 1) FSR = 80h
[INDF] = 10h
GOTO Bank0_LP ; continue
; ** IF DEVICE HAS BANK1 **
MOVLW 0x80
1
FSR++
; W 1st address in GPR bank
[INDF] = 0Ah
MOVWF FSR
; Indirect address register W
Bank1_LP
CLRF INDF0
; address in GPR 0
INCF FSR
; FSR++ (next GPR address)
BTFSS STATUS, C
; skip if (STATUS<0> == 1)
FSR = 00h
MZCET/EEE/EE6008/1
127
GOTO Bank1_LP
; continue
1.
8
SampleProgram
Prog:
Branchtoaddressinnew
page
; W Prog10<15:8>
operator HIGH reads bits <15

movlw HIGH ;Prog10
of pointer
movwf PCLATH
; PCLATH W
; PC<10:0> Prog10<7:0>
goto Prog10; PC<12:11> PCLATH<4:3>
g10:
Prog10 labels some address in program memory

MZCET/EEE/EE6008/1
128
1.
8
SampleProgram
movlw HIGH
Prog20
; W
Computedgoto
Prog20<15:8>
movwf PCLATH
; PCLATH W
movlw LOW Prog20
; W
Prog20<7:0>
movwf PCL
; PCL Prog20<7:0>
; PCH PCLATH<4:0>
g20:
Prog20 labels some address in program memory

MZCET/EEE/EE6008/1
129
1.
8
SampleProgra
ms
btfss f,b
ifelsebranch
; skip one instruction if
; bit b in register f = 1
goto Action2
Ye
s
Action1:
; instructions for Action1
goto Action3
F<b>
=1?
Action
1
Action2:
N
o
Action
2

Action
3
Action3:
MZCET/EEE/EE6008/1
130
1.
8
SamplePrograms
Staticloop
movlw times
; W times
; COUNTER W (times)
movwf COUNTER
Loop:
;
; loop instructions
;
decfsz COUNTER, f
; COUNTER-; COUNTER = 0 skip next
instruction
MZCET/EEE/EE6008/1
; next iteration
131
1..
8
SamplePrograms
Datatableininstructionmemory
movlw HIGH Table

movwf PCLATH
movf INDEX, W
call Table
; Function call returns data at

Table.INDEX
; W Table<15:8>
; PCLATH W
; W INDEX
; Call to subroutine table
;
; return with W 'A'
Table:
retlw
'A'
addwf PCL, f
retlw
'B'
retlw
'C'
; PCL PCL + W = PCL + INDEX

; computed goto
MZCET/EEE/EE6008/1
132
Class Test-1
1. Explain the architecture of PIC16CXX
Series. (15)
2. Explain the classification of
instruction set. (15)
3. Explain the Pipelining Process.(8)
4. Write any four features of PIC 16CXX
series. (2)
5. Write the function of BOR register.(2)
MZCET/EEE/EE6008/1
133

Unit I

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Unit I

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UNIT- I

Introduction to PIC Microcontroller

PIC 16C6x and PIC16C7x Architecture

Program Memory considerations

Register File Structure

PIC -Peripheral Interface Controller

Upgradation of lowend architectures

High performance RISC CPU

Only 35 single word instructions to

Power-up Timer (PWRT) and Oscillator

Timer0: 8-bit timer/counter with 8-bit

Capture is 16-bit, max resolution is 12.5

Pin Diagram of PIC16C6X

Pin out Description of

Pin Diagram of PIC16C6X

Pin Diagram of PIC16C6X

Pin Diagram of PIC16C6X

Pin Diagram of PIC16C6X

Pin Diagram of PIC16C6X

Pin Diagram of PIC16C6X

PinNa PinTy Description

PIC16C6X Device varieties

EPROM type memory

EPROM type memory

ROM program memory

ROM program memory

PIC16C6X Device varieties

The UV erasable version, offered in CERDIP

In addition to the program memory, the

PIC16C6X DEVICE VARIETIES

ck-Turnaround-Production (QTP) Devices

Read Only Memory (ROM) Devices

PIC16C6X DEVICE VARIETIES

1: Higher order bits are from the STATUS register.

PIC16C63/R63/65/65A/R65 BLOCK DIAGRA

1: Higher order bits are from the STATUS register.

PIC16C66/67 BLOCK DIAGRAM

The PIC16CXX device contains an 8-bit ALU

Arithmetic and logic

Working register (W register)

PIC16C7X Core Features:

High-performance RISC CPU

PIC16C7X Core Features:

Power-on Reset (POR)

PIC16C7X Peripheral Features:

Timer0: 8-bit timer/counter with 8-bit

PIC16C7X Peripheral Features:

Pin Diagram of PIC16C7X

Pin Diagram of PIC16C7X

Pin Diagram of PIC16C7X

Pin out Description of

Pin out Description of

PinNa PinTy Description

Pin out Description of

I/O PORTC is a bi-directional I/O port.

PIC16C72 BLOCK DIAGRAM

A twostage pipeline overlaps fetch and

Working Register (W)

Clocking Scheme/Instruction Cycle

Internal division of oscillator clock input as Q1,

An Instruction Cycle consists of four Q cycles

It has three memory blocks.

Program memory Considerations

How to access 2K Program