A MAJOR PROJECT

on

PARITY PRESERVING ADDER/SUBTRACTOR

USING A NOVEL REVERSIBLE GATE

JYOTHISHMATHI INSTITUTE OF TECHNOLOGY & SCIENCE

Presented by
S.Suma
14271D5709

CONTENTS

INTRODUCTION
EXISTING SYSTEM
DISADVANTAGES
PROPOSED SYSTEM
BLOCK DIAGRAM
ADVANTAGES
APPLICATIONS
CONCLUSION
SOFTWARE REQUIREMENT
REFERENCES

INTRODUCTION
power consumption is a major constraint in
designing of VLSI circuits
Reversible logic has received great importance
P2RG.gate
It can work both as a full adder and a full
subtractor

EXISTING SYSTEM
Toffoli gate
MIG gate
NCG gate

DISADVANTAGES
A lot of bit loss which reduces life of the
circuit
Extraction of input from the respective output
is not possible.
High power

PROPOSED SYSTEM
A new 5*5 parity preserving reversible gate,
P2RG is introduced
This gate is one through which means one of
its inputs is also an output

BLOCK DIAGRAM

ADVANTAGES
No information bit loss during computation
Low power dissipation
High speed

SOFTWARE REQUIREMENT
ModelSim 6.4c
Xilinx 13.2

REFERENCES
R. Landauer, Irreversibility and heat generation in
the computing process, IBM journal of research
and development, vol. 5, no. 3, pp.183191, 1961.
C. H. Bennett, Logical reversibility of
computation, IBM journal of Research and
Development, vol. 17, no. 6, pp. 525532, 1973.
R. P. Feynman, Quantum mechanical computers,
Foundations of physics, vol. 16, no. 6, pp. 507531,
1986.
E. Fredkin and T. Toffoli, Conservative logic.
Springer, 2002.