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HJSChapter11PowerGridandClockDesign
Forbackgroundinformationrefertochapter5ofthetextbook
Design Example
VDD ( FractionalNoiseBudget )
I DD
Vdd
n4
n3
< Vdd
n2
n1
n8
n5
n6
n7
If we connect bottom
portion of grid to top
portion, the IR drop is
reduced significantly
However, this is only
one part of the
problem
We must also
examine
electromigration
n4
n3
n2
n1
n8
n5
n6
n7
10
11
12
13
14
To estimate required decap value, run SPICE on patch of chip area with
power grid, part of logic block, and sprinkle of decaps
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17
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Block A
Single Trunk
Block B
Block A
Block B
Multiple Trunks
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Block A
Block B
Double-Ended Connections
Block A
Block B
Wider Trunks
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Interleaved Vdd/Vss
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Clocked D Flip-flop
Very useful FF
Widely used in IC design for temporary storage of data
May be edge-triggered (Flip-flop) or level-sensitive (transparent
latch)
data
CK
Clk Q
output
Qn+1
0
1
0
1
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In
Out
Clk
In
Out
CLK
Latch
In
Clk
Out
In
Out
CLK
Flip-Flop
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Alternative View
Clocks serve to slow down signals that are too fast
Flip-flops / latches act as barriers
Latch
Flip-Flop
DQ
DQ
Clk
Ld
Clk
Soft Barrier
Clk 0->1
Clk=1
DQ
DQ
Ld
Ld
Clk
Hard Barrier
Clk
With a latch, a signal can propagate through while the clock is high
With a Flip-flop, the signal only propagates through on the rising edge
Flip-flops consist of two latch like elements (master and slave latch)
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Clocking Overhead
FF and Latches have setup and hold times that must be satisfied:
Flip Flop
will work
wont work
Din
Clk
Latch
may work
Din
Thold
Qout
Tsetup
Clk
Thold
Qout
Tsetup + Tclk-q
Td-q
If Din arrives before setup time and is stable after the hold time, FF will work; if Din
arrives after hold time, it will fail; in between, it may or may not work; FF delays the
slowest signal by the setup + clk-q delay in the worst case
Latch has small setup and hold times; but it delays the late arriving signals by Td-q
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Clock Skew
Not all clocks arrive at the same time, i.e., they may be skewed.
SKEW = mismatch in the delays between arrival times of clock edges at FFs
SKEW causes two problems:
Tclk-q
Fix critical path
Logic
Td
Flop
Early
Td=0
Flop
Late
Flop
Flop
Tsetup
Insert buffer
Delay elements
Early
Late
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Skew Tclk-q
Tlogic
CLOCK
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DQ
Clk
Clk
DQ
Clk
Clk
Ideal Vdd
- Low delay
- Low skew
Delay (latency)
Skew
Conservative Vdd
- High delay
- Low skew
Much of the power (and the skew) occurs in the final drivers due
to the sizing up of buffers to drive the flip-flops
Key to reducing the power is to examine equation CV 2f and reduce
the terms wherever possible
VDD is usually given to us; would not want to reduce swing due
to coupling noise, etc.
Look more closely at C and f
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clock
shield
Signal 1
clock
Signal 2
Clock Design
Tree
Main clock
driver
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Clock Configurations
H-Tree
Clock Configurations
Grid
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Normal Distribution
Jitter
1
0.8
0.6
Prob
Series1
0.4
0.2
0
-3
-2
-1
sigma
Clock
edge
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Old methodology
Route clock
Route rest of nets
Extract clock parasitics
Perform timing verification
Balance clock by snaking
route in reserved areas
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