Before diving into the working of D Flip Flop, lets start

with Inverters and Transmission Gates

INVERTER
i/p = 0 pMOS alone is ON
o/p driven by VDD i.e. O/p = 1
i/p = 1 nMOS alone is ON
o/p gets discharged i.e. o/p = 0

TRANSMISSION GATE
nMOS and pMOS connected in parallel.
Inputs to both MOSFETs are
complementary.
Bidirectional can carry current in either
directions.

Depending on whether or not there is a voltage on the gate, the

connection between the input and output is either lowresistance or high-resistance, respectively. Ron = 100 ohm and
Rof > 5 megohm. This can efectively isolate the output from the
input.
Whenever both, nMOS and pMOS both are turned on, it passes
any signal '1' or '0' equally well without degradation.
The use of transmission gates eliminates the undesirable
threshold voltage efects which give rise to loss of logic levels.

A sneak peek into transistorlevel structure of D flip-flop

Figure: 1

Working of D flip-flop...

Figure: 2 (The darkened lines show the conducting path)

Initially say, D = 0 and CLK is LOW.

Hence ....... Z=0

Currently, neglecting the latching circuit on RHS.

Working of D flip-flop(contd.)

Now, CLK goes HIGH

LHS latching circuit is enabled. It latches 1 which results in Q=0 (which is what it should be for
D = 0). It is to be noted that o/p arrives at positive edge of CLK. Hence its a positive edge
triggered flip flop.

Working of D flip-flop(contd.)

When CLK goes LOW, RHS latching circuit is enabled and there is no change in o/p

Any change in i/p is reflected at node Z which is reflected at the o/p at next positive edge of
CLK.

In summary, if D changes then the change would reflect at node Z when CLK is LOW and
would appear at the o/p when CLK goes HIGH.

Setup time is defined as the minimum amount of

time BEFORE the clocks active edge by which the data
must be stable for it to be latched correctly. Any
violation in this minimum required time causes
incorrect data to be captured and is known as setup
violation.

Hold time is defined as the minimum amount of time

AFTER the clocks active edge during which the data
must be stable. Any violation in this required time
causes incorrect data to be latched and is known as
hold violation.

Why SETUP TIME?

Initially suppose D=0 and CLK is LOW. The i/p D will be reflected
at node Z. So, the time it takes for i/p D to reach node Z i.e.
traverse the path D V W X Y Z is called the SETUP time
and this is the reason why SETUP time comes into picture.
The requirement is that, before the LHS latching circuit is enabled
i.e. CLK becomes HIGH, data at node Z should be stable and
correct. If this is not the case then SETUP violation is said to be
occurred.
.

WHAT IF THE SETUP-VIOLATION OCCURS???

If the i/p D is changed within the setup window the change in D
will not be reflected completely at node Z by the time CLK goes
HIGH. Therefore node Z will neither be at logic 0 nor logic 1 at that
instant. This is termed as Metastability.
Suppose, there's a metastable value at node Z due to setup
violation at the moment when CLK goes HIGH. At this very
moment the LHS latching circuit kicks in and it takes some time to
latch the stable value which may or may not be the correct one.
( We'll soon see how). This latched value is proceeded to the o/p Q.
Thus, there is an increase in clock to Q(C2Q) delay.
Hence its necessary for the D input to remain stable inside the
setup window for proper latching operation once the active clock
edge kicks in. Thus the setup time is nothing but the sum total of
the delays introduced when D input traverses the path D V W

Why Hold Time?

Its the time w.r.t. the active clock edge, taken for i/p D to reach the node
W. Note: The Clock is given to the Tx gate and the data is given to the
inverter (or any other logic sitting before Tx gate and is a part of the flipflop).
The Transmission Gate takes time to switch of and on. Moreover, the CLK
and CLK bar given to the Tx gate comes after ramping up of the CLK
signal and not directly. Hence, there is a finite delay b/w the CLK and CLK
bar and thus the Tx gate as such takes some time to switch of and it
requires the i/p data to remain stable during this period. This is known as
HOLD Time.

WHAT IF THE HOLD-VIOLATION OCCURS???

While the Tx gate is switching of, the i/p data D is
expected to be stable, but if it undergoes any
transition then the node W gets afected since Tx gate
VW and ZW are both partially open and theoretically
driving node W to both logic 1 and 0 at the same time.
Again this causes node W to become metastable. This
leads to increase in C2Q delay.
There can be positive, zero and negative Hold time
depending upon the delay of the logic sitting before
the transmission gate.
Lets view them....

The adjacent diagram

illustrates the concept of
diferent types of HOLD
TIME.

TTX > Tinitial

Positive Hold Time

Zero Hold Time

TTX = TInitial
Negative Hold Time

METASTABILITY
How to determine whether the signal is
logic HIGH or logic LOW?
Voltage range and Threshold
The voltage levels falling between 0V to
Vol is taken to be logic LOW & the
TTL Voltage Levels
voltages lying between Voh to 5V is
taken to be logic HIGH. Any node
having voltage levels between Voh and
Vol is said to be in No Man's Land (in
other words Metastable).
CAUSE:
setup or hold violations for which the afected nodes doesn't get enough
time to settle to a stable voltage level.
CONSEQUENCES:
In flip flops, this leads to increase in C2Q delay and eventually leading to
capture of wrong data.

How does C2Q delay increase?

Since latching circuit is back to back inverter(o/p of one inverter is i/p to
the other inverter), the I/O characteristic is derived from the
characteristic of single inverter.

Figure Missing!!!

If the value at node W is

not exactly 0 or 5 but
somewhere in between
2.5-5, then the latching
action would pull node X
to logic LOW or 0. But it
certainly takes some
more time as it requires
to complete some
latching cycles before
reaching the stable value
The LHS latching circuit is enabled at the
of 0V.
positive edge of clock and since the latching
circuit takes more time to latch a stable value
at node X when node Z is metastable, we can
see that C2Q delay increases.
If such delays accumulate over flops it may so happen that a data
signal is missed by the clock edge at which it was suppose to be
captured.
Imagine the case in a Counter Module !!!!

WAYS TO CORRECT SETUP AND HOLD

VIOLATIONS
SETUP VIOLATION:
Reduce the working frequency of the chip.
Reduce the combinational logic delay between the
talking flops.
Skew can be introduced between the flops
HOLD VIOLATION:
Increase the combinational delay between the talking
flops.
Skew between the flops can be reduced.

How to make the D f/f Asynchronous reset(rb)

enabled??
To introduce asynchronous reset the following points need to be
satisfied:
I.Asynchronous Reset works independent of the clocks state.
II.Whenever Reset is asserted, there should not be any short between V dd
& Vss (source & drain).
III.When Reset is de-asserted, the flip-flop should continue to latch logic
0 until the next active clk edge appears.

Asynchronous reset enabled

Asynchronous reset (rb) enabled D f/f

1 satisfies (I) condition.

2 satisfies (II) condition.
3 satisfies (III) condition and 4 & 5 satisfy the (II) condition for 3.

A Better D flip-flop to manufacture

Fabrication is cheaper if the structure is symmetrical, hence the
following changes.

The above D f/f has only 2 changes Guess What!!!

Firstly, to achieve similarity b/w 2 latching circuits, an inverter is

introduced between them.
Secondly, the transmission gate and the inverter have been merged
together to one single unit.

So, basically the reset logic is built upon the following basic Df/f
structure:

In addition to reset, preset can also be integrated into the D f/f. Lets
take a look!!!

DFF with asynchronous reset & preset

SDI = scan data input, SE = scan enable, D = input data, rb = reset
bar, pb = preset bar

D f/f with scan inputs

Replacing the inverter, prior to the first Transmission gate with the
structure above will make the D f/f scannable . Now we can control
the SDI Scan Data Input via SE(active high) Scan Enable.

Now, having looked into the working of D flip-flop, setup

and hold of latch and flip-flop, lets understand these timing
concepts between talking flops

SETUP AND HOLD

BETWEEN TALKING
FLOPS

Consider the adjacent figure

depicting a flop to flop path in the
same domain with some
combinational logic between them.
We will now calculate the setup
and hold time slacks in the design
based on the given timing
parameters.
The data required time for the
capture flop B to meet setup is:
Data Required time = (Clock
Period + Clock Insertion Delay +
Setup and Hold time illustration - Full cycle transfer
Clock Skew - Setup time of the
flop) = 8 + 2 + 0.25 -0.1 =
10.15 ns
The data arrival time from the launch flop is:
Data Arrival time = (Clock Insertion Delay + CK->Q Delay of the
launch flop + Combinational logic Delay) = 2 + 0.1 + 5 = 7.1 ns.
Setup slack is
Setup Margin = Data Required Time - Data Arrival Time = 10.15 7.10 = 3.05 ns

Similarly for hold checks

assuming the hold time
requirement of the flop B is
100 ps, the data expected
time is:

Setup and Hold time illustration - Full cycle transfer

Data expected time =

(Clock Insertion Delay +
Clock skew + Hold time
requirement of flop) = 2 +
0.25 +0.1 = 2.35 ns.

So the hold time slack is

Hold Margin = Data Arrival time - Data expected time =
7.10 - 2.35 = 4.85 ns

Consider the case where the clock to flop B is inverted (or that the flop
is negative edge trigerred). In this particular case, the relevant edges
for setup/hold are as shown in the figure below.

Setup and Hold time illustration - Half cycle transfer

In this scenario, the setup margin considering all the other parameters to
be the same is
Data Required time = (half_clock_period + clock insertion delay + Ck>Q delay of flop A - Setup time required for flop B) = 4 + 2 + 0.25 -0.1 =
6.15 ns
Since the Data Arrival time remains the same, i.e.
Data Arrival time = (Clock Insertion Delay + CK->Q Delay of the launch
flop + Combinational logic Delay) = 2 + 0.1 + 5 = 7.1 ns. there is a setup
violation of
Setup violation = 6.15 ns - 7.10 ns = -1.05 ns

There is no hold violation since the data arrival time remains the time but
the data expected time is any time after (Clock skew + Hold time
requirement of flop B)
Data expected time = 0.25 + 0.1 = 0.35 ns
Hold Margin = 7.10 - 0.35 = 6.75 ns

Stop Observing, Start Pondering

FEW QUESTIONS ENJOY

Maximum Allowable Clock Skew