MCBSD 14.7.2016 New

EE6008
MICROCONTROLLER
BASED SYSTEM DESIGN
BE-EEE 07 SEMESTER
Collected by
C.GOKUL
AP/EEE
Velalar College of Engg & Tech,Erode
Syllabus
EE6008 MICROCONTROLLER BASED SYSTEM
DESIGN
UNIT-1
INTRODUCTION TO PIC
MICROCONTROLLER
UNIT-1 Syllabus
INTRODUCTION TO PIC MICROCONTROLLER
Introduction To PIC Microcontroller

PIC 16C6x And PIC16C7x Architecture
PIC16cxx
Pipelining
Program Memory Considerations
Register File Structure
Instruction Set
Addressing Modes
Simple Operations
Introduction to
PIC
Microcontroller
What is PIC?
The term PIC or Peripheral Interface Controller,
has been coined by Microchip Technology Inc.
Low-end range, mid-range and high end range of
controllers.
PIC Architecture: Background

Were used to the Von-Neuman Architecture
Used in: 80X86 (PCs), 8051, 68HC11, etc.)
Only one bus between CPU and memory
RAM and program memory share the same bus and
the same memory, and so must have the same bit
width
Bottleneck: Getting instructions interferes with
accessing RAM
Memory
CPU
(&
Data)
PIC Architecture: Background

PICs use the Harvard Architecture
Used mostly in RISC CPUs (well get there)
Separate program bus and data bus: can be
different widths!
For example, PICs use:
Data memory (RAM): a small number of 8bit
registers
Program memory (ROM): 12bit, 14bit or 16bit
wide (in EPROM, FLASH, or ROM)
Memory
Memory
(Data)
CPU
12
14
16
(Program
)
Von Neumann & Harvard

Architecture
Von Neumann
Architecture:
Fetches instructions and

data from a single memory
space
Limits operating bandwidth
Harvard Architecture:
2006 Microchip Technology Incorporated. All Rights Reserved.
101 ASP
Uses two separate memory

spaces for program
instructions and data
Improved operating
bandwidth
Allows for different bus
widths
Slide
10
CISC
Traditionally, CPUs are CISC
Complex Instruction Set Computer (CISC)
Used in: 80X86, 8051, 68HC11, etc.
Many instructions (usually > 100)
Many, many addressing modes
Usually takes more than 1 internal clock cycle
(T cycle) to execute
Example:
MC68HC05:
0x55
LDAA
1000
1100
01010101
2 bytes, 2 cycles
RISC
PICs and most Harvard chips are RISC
Reduced Instruction Set Computer (RISC)
Used in: SPARC, ALPHA, Atmel AVR, etc.
Few instructions (usually < 50)
Only a few addressing modes
Executes 1 instruction in 1 internal clock cycle
(Tcyc)
Example:
PIC16CXXX:
MOVLW 0x55
1100XX 01010101
1 word, 1 cycle
What is New in PIC?

High performance RISC CPU with 35 no. of
instruction set only
Harvard Architecture
Pipelined Instructions
And a large number of Peripherals In-built
PIC Microcontrollers
PIC =>Peripheral Interface Controller

Microchip Technology
single-chip microcontrollers
8-bit microcontrollers
Assembler and simulator
Low - end PIC Architectures

12-bit wide instructions
functions.
limited program memory
with
basic
I/O
applications
requiring
simple
interface
functions and small program & data memories
12C5XX
16C5X
16C505
Mid range PIC Architectures

low-end architectures + more number of
peripherals + more number of registers + more
data/program memory
16C6X
16C7X
16F87X
Program memory type
C = EPROM
F = Flash
RC = Mask ROM
Popularity of the
PIC microcontrollers
Speed:
Harvard
Architecture,
RISC
architecture, 1 instruction cycle = 4 clock
cycles
Instruction set simplicity: 35 instructions
Power-on-reset and brown-out reset
A watch dog timer (user programmable)
Four optional clock sources
Low power crystal, Mid range crystal, High
range crystal, RC oscillator (low cost)
Popularity of the
PIC microcontrollers
Programmable timers and on-chip ADC
Up to 12 independent interrupt sources
Powerful output pin control (25 mA (max.)
current sourcing capability per pin.)
EPROM/OTP/ROM/Flash memory option
I/O port expansion capability
Free assembler and simulator support from
Microchip at www.microchip.com
CPU Architecture
Harvard Architecture
instruction fetch & operation on data/accessing
of variables simultaneously
PIC Memory Organisation

Program memory address
= 13 bits
Can address up to 8k
Program counter = 13-bit
PIC 16C6X => 2k (11 bits)
PIC16C7X => 4k (12 bits)
program memory map of PIC16C74A
Specifications
Popular PIC microcontrollers
Special purpose register file (similar to SFR
in 8051).
PIC Microcontroller Clock

Can operate upto 20MHz
One instruction cycle (machine cycle)
consists of four clock cycles
Instructions : PC content no change 1

instruction cycle
PIC 16C6x &

PIC16C7x
Architecture
Architecture of PIC16C74A
PC=13 bit
PM=14 - bit word
Program Memory
capacity
= 8k x 14 bit
Each instruction
of PIC 16C74A is
14 - bit long.
Port Structure and Pin Configuration
CPU registers
W, the working register
STATUS Register
C = Carry bit
DC = Digit carry (same as auxiliary carry)
Z = Zero bit
NOT_TO and NOT_PD - Used in conjunction with PIC's sleep mode
RP0- Register bank select bit used in conjunction with direct addressing mode
FSR Register
(File Selection Register, address = 04H, 84H)
- 8-bit register - data memory address pointer
- indirect addressing mode.
CPU registers
INDF Register
(INDirect through FSR, address = 00H, 80H)
INDF is not a physical register.
- Accessing INDF access is the location pointed to
by FSR in indirect addressing mode.
PCL Register
(Program Counter Low Byte, address = 02H,
82H)
- lower 8-bits of the 13-bit program counter.
- both readable and writable register.
CPU registers
PCLATH Register
(Program Counter Latch, address = 0AH, 8AH)
Program Counter Stack

- An independent 8-level stack
- Organized as 8x13bit registers.
Pipelinin
g
Pipelining of instruction fetch successive

addressing
Introduction of extra cycle for a jump /

goto instruction
Register
File
Structure
Register File
Map
Bank - 0 and Bank -1

Some Registers in
both
Changes occur in both
Register File Concept

Data Memory
(Register File)
w
All peripherals are

mapped into data
memory as a series of
registers
Orthogonal Instruction
Set: ALL instructions
can operate on ANY
data memory location
The Long Word

Instruction format
allows a directly
addressable register file
08h
09h
Data Bus
Bus
Data
Register File Concept:

All of data memory is
part of the register file,
so any location in data
memory may be
operated on directly
07h
ALU
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
W
W
Decoded Instruction
from Program Memory:
Opcode
Opcode d
d
Arithmetic/Logic Function
to be Performed
Result
Destination
Address
Address
Address of Second Source
Operand
101 ASP
Slide
36
Instructio
n Setoverview
Instruction Set Overview
101 ASP
Slide
38
101 ASP
Slide
39
101 ASP
Slide
40
PIC16 Instruction Set

addwf
addwf
andwf
andwf
Byte
Byte Oriented
Oriented Operations
Operations
f,d
f,d Add
Add W
W and
and ff
f,d
f,d
clrf
clrf ff
clrw
clrw -comf
comf f,d
f,d
decf
decf f,d
f,d
decfsz
decfsz
incf
incf f,d
f,d
incfsz
incfsz
rlf
rlf
rrf
rrf
xorwf
xorwf f,d
f,d
Bit
Bit Set
Set ff
Bit
Bit Test
Test f,f, Skip
Skip ifif Clear
Clear
Clear
Clear W
W
Complement
Complement ff
f,d
f,d
Decrement
Decrement ff
Decrement
Decrement f,f, Skip
Skip ifif 00
addlw
addlw
andlw
andlw
f,d
f,d
Increment
Increment ff
Increment
Increment f,f, Skip
Skip ifif 00
call
call kk
clrwdt
clrwdt
Inclusive
Inclusive OR
OR W
W with
with ff
Move
Move ff
goto
goto
iorlw
iorlw
Move
Move W
W to
to ff
No
No Operation
Operation
movlw
movlw
retfie
retfie --
Rotate
Rotate Left
Left ff through
through Carry
Carry
Rotate
Rotate Right
Right ff through
through Carry
Carry
retlw
retlw kk
return
return
Subtract
Subtract W
W from
from ff
Swap
Swap nibbles
nibbles in
in ff
sleep
sleep -sublwk
sublwk
Go
Go into
into standby
standby mode
mode
Subtract
Subtract W
W from
from literal
literal
Exclusive
Exclusive OR
OR W
W with
with ff
xorlw
xorlw kk
Exclusive
Exclusive OR
OR literal
literal with
with W
W
ff
f,d
f,d
f,d
f,d
subwf
subwf
swapf
swapf
f,b
f,b
f,b
f,b
btfsc
btfsc f,b
f,b
btfss
Bit
btfss f,b
f,b
Bit Test
Test f,f, Skip
Skip ifif Set
Set
Literal
Literal and
and Control
Control Operations
Operations
iorwf
iorwf f,d
f,d
movf
movf f,d
f,d
movwf
movwf
nop
nop --
AND
AND W
W with
with ff
Clear
Clear ff
bcf
bcf
bsf
bsf
Bit
Bit Oriented
Oriented Operations
Operations
Bit
Bit Clear
Clear ff
f,d
f,d
f,d
f,d
101 ASP
kk
kk
Add
Add literal
literal and
and W
W
AND
AND literal
literal with
with W
W
--
Call
Call subroutine
subroutine
Clear
Clear Watchdog
Watchdog Timer
Timer
kk
kk
Go
Go to
to address
address
Inclusive
Inclusive OR
OR literal
literal with
with W
W
kk
--
Move
Move literal
literal to
to W
W
Return
Return from
from interrupt
interrupt
Return
Return with
with literal
literal in
in W
W
Return
Return from
from Subroutine
Subroutine
Slide
41
PIC16 Visual Interpreter

0x0A ,
ADDLW
Hex
Dec
Data
Bus
Literal Data from

Instruction Word
ALU
FF
FF
FF
FF
FF
W
Register
Register File
FF
FF
FF
18
FF
FF
Bin
Execute
101 ASP
Reset
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
STATUS
2 1 0
1 0 0
Z DC C
Slide
42
PIC Microcontroller
Instruction Set
Outline
Instruction
set
Instruction description
Assembler directives
Instruction Set
PIC16Cxx
@
PIC16Fxx: 14bit word
(opcode)
Byte-oriented,
bit-oriented &
literal and
control
Instruction Set
cont
Instruction
Descriptions
ADDLW K
Add
the literal value K to register WREG and

put the result back in the WREG register
(W) + k (W)
K is an 8-bit value: 0-255 (decimal), 00-FF
(hex)
L: literal (actual value)
Affect STATUS bits: C, DC, Z
ADDLW K
Instruction: ADDLW
cont
15H
Before
After
W = 10H
W = 25H
ADDWF f, d
Add
together contents of WREG and a file

register location (SFR @ GPR).
Put the result in the register WREG if d = 0
otherwise it is stored back in register f.
(W) + (f) (d)
0 f 127, d [0, 1]
Affect STATUS bits: C, DC, Z
ADDWF f, d
Instruction: MOVLW
17H
ADDWF 5H, 0
Before
After
W = 0H
5H = 0H
W = 17H
5H = 0H
cont
MOVF f, d
Move the content of f register upon the status of
d
(f) (d)
Affect bit Z of STATUS register
Instruction: MOVF
Before
W = 09AH
FSR = 0H
FSR, 0
After
W = value in FSR register

Z=1
MOVLW
Load k literal into WREG register

k (W)
Dont cares will be assembled as 0s
Not affect bit of STATUS register
Instruction: MOVLW
Before
W = 09AH
After
W = 5AH
5AH
MOVWF f
Move data from WREG register to f register
(W) (f)
Instruction: MOVWF
Before
PORTB = 00H
W = 09AH
PORTB
After
PORTB = 09AH
W = 09AH
ANDLW k
Logical
AND k literal with the content of WREG

register & the result is placed in the WREG register
(W) AND k (W)
Affect Z bit of STATUS register
Instruction: ANDLW
Before
W = A3H
5FH
After
W = 03H
ANDWF f, d
AND the WREG register with f register

(W) + (f) (d)
Affect Z bit of STATUS register
Instruction: ANDWF
Before
W = 17H
FSR = 0C2H
FSR, 1
After
W = 17H
FSR = 02H
BCF
f, b
Clear bit b in file register

0 (f<b>)
Not affect on STATUS register
Instruction: BCF STATUS, 5

Before
After
STATUS = 0A7H STATUS = 087H
BSF
f, b
Set bit b in f register

1 (f<b>)
Instruction: BSF INTCON, 7

Before
After
INTCON = 0BH
INTCON = 08BH
BTFSS f, b
Execute the next instruction if bit b in file register f is

0, otherwise discard executing next instruction
2-cycle instruction
Instruction: H BTFSS STATUS, 2
I GOTO LOOP
J
Before
PC = address H
After
PC = Add. J if STATUS<2> = 1,
PC = Add. I if STATUS<2> = 0
BTFSC f, b
Execute the next instruction if bit b in file register f is

1, otherwise discard executing next instruction
2-cycle instruction
Instruction: H BTFSC PORTA, 3
I GOTO LOOP
J
Before
After
PC = address H
PC = Add. J if PORTA<3> = 0,
PC = Add. I if PORTA<3> = 1
CALL k
Call subroutine
(PC) + 1 TOS (top of stack)
k PC<10:0>
(PCLATCH<4:3>) PC<12:11>
2-cycle instruction
Instruction: SO CALL THEN
Before
After
PC = add. SO
PC = add. THEN;
TOS = add. SO+1
CLRF f
Clear the content of f register
00h (f)
1 Z
Instruction: CLRF PORTA

Before
PORTA = 5AH
After
PORTA = 00H
Z=1
CLRW
Clear the content WREG register
00h (W)
1 Z
Instruction: CLRW
Before
W = 5AH
After
W = 00H
Z=1
COMP f, d
Complement the content of f register
(f) (d)
Instruction: COMP ONE, 0

Before
ONE = 13H
W = 02H
After
ONE = 13H
W = 0ECH
DECF f, d
Decrease f register
(f) 1 (d)
Instruction: DECF CNT, 1

Before
CNT = 01H
Z=0
After
CNT = 00H
Z=1
DECFSZ f, d
Decrease f register and skip the next instruction if the result is 0;

otherwise execute the next instruction
(f) 1 (d), skip if result = 0
2-cycle instruction
Instruction:
HERE DECFSZ CNT, 1

GOTO HERE
CONT
..
Before
After
PC = add. HERE
CNT = CNT - 1
PC = add. CONT if CNT = 0;
PC = add. HERE + 1 if CNT 0
GOTO k
Unconditional branch
k PC<10:0>
(PCLATCH<4:3>) PC<12:11>
2-cycle instruction
Instruction: HERE
GOTO THERE
THERE
Before
PC = add. HERE
After
PC = add. THERE
INCF f, d
Increase the content of f register

(f) + 1 (d)
d is destination
Instruction: INCF SATU, 1

Before
SATU = 0FFH
After
SATU = 00H
Z=1
INCFSZ
f, d
Increase the content of f register and skip the next instruction if the
result is 0; otherwise execute the next instruction
(f) + 1 (d), skip if result = 0
2-cycle instruction
Instruction: HERE INCFSZ CNT, 1

GOTO
loop
CONT
..
Before
After
PC = add. HERE
CNT = CNT + 1
PC = add. CONT if CNT = 0;
else add. HERE + 1
IORLW k
Inclusive OR literal k with the content of WREG
register
(W) OR k (W)
Instruction: IORLW
Before
W = 09AH
Z=?
35H
After
W = 0BFH
Z=0
IORWF f, d
Inclusive OR the content of WREG register with f
register
(W) OR (f) (d)
Instruction: IORWF
Before
RESULT = 13H
W = 91H
RESULT, 0
After
RESULT = 13H
W = 93H
Z=0
NOP
No operation
Instruction: NOP
RETFIE
Return from interrupt
TOS PC
1 GIE (Global Interrupt Enable)
Instruction: RETFIE
Before
After
PC = TOS
GIE = 1
RETLW
Return with loading literal k onto WREG

register, k (W)
TOS PC
Instruction: RETLW
Before
W = 09AH
088H
After
W = 088H
RETURN
Return from subroutine
POP the TOS and load into the PC
2-cycle instruction
Instruction: RETURN
Before
After
PC = TOS
RLFf, d
Rotate left f through carry

Affect bit C of STATUS register
Instruction: RLF REG, 1

Before
After
REG = 1111 1111 = 0FFH

C=0
REG = 1111 1110 = 0FEH

C=1
RRF f, d
Rotate right f through carry

Affect bit C of STATUS register
Instruction: RRF REG, 1

Before
After
REG = 1111 0111 = 0F7H

C=0
REG = 0111 1011 = 07BH

C=1
SLEEP
00h WDT
0 WDT prescalar
1 TO
0 PD
Affect TO & PD bits of STATUS register
Instruction: SLEEP
SUBLW
Subtract WREG register (2s complement) from literal k

and put the result onto WREG register
k (W) (W)
Affect C, DC & Z bits of STATUS register
Instruction: SUBLW
02H
Before
After
W = 01H
C=?
Z=?
W = 01H
C=1
Z=0
SUBWF f, d
Subtract WREG register (2s complement) from f register

(f) (W) (d)
Affect C, DC & Z bits of STATUS register
Instruction: SUBWF
02H, 0
Before
After
W = 01H
F = 05H
C=?
Z=?
W = 04H
F = 05H
C=1
Z=0
SWAPF f, d
Exchange the upper & lower nibbles of f register
(f<3:0) (d<7:4>), (f<7:4) (d<3:0>)
Not affect STATUS register
Instruction: SWAPF
Before
ON = 0F4H
W = 09AH
ON, 1
After
ON = 04FH
W = 09AH
XORLW k
Exclusive OR (XOR) the content of WREG
register with k literal
(W) XOR k (W)
Store the result in WREG register
Instruction: XORLW
Before
W = 0B5H
0AFH
After
W = 01AH
XORWF f, d
Exclusive OR (XOR) the content of WREG
register with f register
(W) XOR (f) (d)
Instruction: XORWF
Before
REG = 0AFH
W = 0B5H
REG, 1
After
REG = 01AH
W = 0B5H
PIC16
Addressing
Modes
Addressing Modes
Direct Addressing
-through a 9-bit address (7 bits of direct address of an
instruction with two bits (RP1, RP0) from STATUS register)
Any access to SFR registers is an example of direct
addressing.
Addressing Modes
Indirect Addressing
-derives it from IRP bit of STATUS and FSR registers.
-Addressed location is accessed via INDF register which
in fact holds the address indicated by a FSR.
One general purpose register (GPR) at
address 0Fh contains a value of 20.
By writing a value of 0Fh in FSR register

we will get a register indicator at
address 0Fh, and by reading from INDF
register, we will get a value of 20, which
means that we have read from the first
register its value without accessing it
directly (but via FSR and INDF).
Program
Memory
Considerations
Program Memory Organization
Program memory is
divided into four 2k14
pages
0000h
14-bits
Reset
Reset Vector
Vector
0004h
Interrupt
Interrupt Vector
Vector
Required to maintain
single word/single
cycle execution
0800h
Paging is only a
concern when using
the call or goto
instructions, or when
directly modifying the
program counter
1000h
2k
Page
Page 00
PCH
PCH == 00h
00h
Page
Page 11
2k
Page
Page 22
2k
Page
Page 33
2k
PCH
PCH == 08h
08h
PCH
PCH == 10h
10h
1800h
PCH
PCH == 18h
18h
1FFFh
101 ASP
Slide
89
Program Counter
PCH
Program Counter
PCL
12
11
10
00
00
00
00
00
00
00
00
00
00
00
00
00
13-bit PC can access up to 213 = 8192 words

Contains address of NEXT instruction (pipelining)
Lower byte accessible in data memory as PCL
Upper byte indirectly accessible via PCLATH
Runs freely across page boundaries
Events that modify PC out of sequence:
Interrupts
Instructions: CALL, GOTO, RETURN, RETLW, RETFIE
Any instruction that uses the PCL register as an operand
101 ASP
Slide
90
PC Absolute Addressing
CALL and GOTO Instructions:
13
12
11
Opcode
Opcode
00
00
00
00
00
00
00
00
00
00
00
Jump to another program memory location out of PC sequence

Call a subroutine
Used by the CALL and GOTO instructions
PC Absolute Addressing (Program Memory)
10
11-bits of the required 13 address bits are encoded in the

instruction
2 additional bits will come from the PCLATH register
Used when performing Computed Goto operation
Address to jump to is calculated by the program

Computed address is written directly into the Program Counter
101 ASP
Slide
91
14-Bit CALL or GOTO Instruction in Program Memory
13
12
11
Opcode
Opcode
10
00
00
00
00
00
00
00
00
00
00
00
Slide
92
PCLATH Register in Data Memory

7
--
--
--
00
00
00
00
00
11-Bits From Instruction
2-Bits From PCLATH

12
11
10
00
00
00
00
00
00
00
00
00
00
00
00
00
PCH
PCH
PCL
PCL
13-Bit Program Counter
101 ASP
Example: Jumping to code located in a different program memory page.

PCLATH Register
CALL Instruction in Program Memory
--
--
--
00
00
00
00
00
W Register
13
12
11
Opcode
Opcode
10
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
Program Counter - PCH:PCL
FF
MySubroutine
--
00
00
00
00
00
00
00
org 0x0020
movlw
HIGH MySubroutine
movwf
PCLATH
call
MySubroutine
org 0x1250
<do something useful>
return
101 ASP
Slide
93
CALL / RETURN Stack

0020
0021
0022
0023
0024
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
100A
MySub1
MySub2
MySub3
MySub4
movlw HIGH
MySub1
movwf PCLATH
call
MySub1
call
MySub4
bsf PORTB,7
bsf PORTB,0
call
MySub2
return
bsf PORTB,1
call
MySub3
return
bsf PORTB,2
return
bsf PORTB,3
call
MySub2
return
101 ASP
13-bit Program Counter
0020
0
1
2
3
4
5
6
7
13-bit x 8-Level
Return Address Stack
Slide
94
PC Relative Addressing
FF
W Register
To write to PC:
Write high byte to
PCLATH
Write low byte to PCL
(PCH will be loaded with
value from PCLATH)
8-bit Data Bus
PCLATH
FF
PCH
PCL
FF
movlw
movwf
movlw
movwf
101 ASP
FF
HIGH 0x1250
PCLATH
LOW 0x1250
PCL
Slide
95
PC Relative Addressing: Lookup

Table
PIC MCU
ORG 0x0020
;Page 0
movlw HIGH SevenSegDecode
Example: Use a lookup table
movwf PCLATH
with relative addressing to
movlw .5
retrieve the bit pattern to
call
SevenSegDecode
movwf PORTB
display a digit on a 7segment LED
ORG 0x1800
;Page 3
SevenSegDecode:
addwf PCL,f
retlw b00111111 ;0
retlw b00000110 ;1
retlw b01011011 ;2
retlw b01001111 ;3
retlw b01100110 ;4
retlw b01101101 ;5
retlw b01111101 ;6
retlw b00000111 ;7
retlw b01111111 ;8
retlw b01101111 ;9
101 ASP
Slide
96
Simple
operation
Programs
The following example explains the I/O port

programming.
Example 1:
MOVLW 0x0
MOVWF TRISB ; make the Port B an output port.
L1: MOVLW 0x55 ; WREG = 55
MOVWF PORTB ; Move 55 into portB.
CALL DELAY
MOVLW 0X AA
MOVWF PORTB ; Move AA into portB
CALL DELAY
GO TO L1
This program alternately loads Port B with 55 and AA.
Example 2: In this example Port B and

PORT C are used to transfer the data
continuously.
MOVLW B 00000000 ; WREG = 00000000(Binary)
MOVWF TRISB
; Port B an out port
MOVLW B 11111111
;WREG = 11111111 (Binary)
MOVWF TRISC
; Port C input Port
L2 MOVF PORTC , W
;Move data from Port C to WREG.
Addlw 5
; Add literal 5 to it.
MOVWF PORTB
; send it to Port B
GOTO L2
; Continue the loop.
Example 3 :
L2
CLRF TRISB
; Clear TrisB( Port B is made out port)
SETF TRISC
; Set TRISC, (Port C is made Input port)
: MOVF PORT C ,W ; Get data from Port C.
ADDLW 5
; Add literal 5
MOVWF PORT B
; Send it to Port B
BRA L2
; Branch to Loop L2
So , it is clear that unless the TRIS bits are activated by putting a 1 ,the
data will not be transferred to WREG from the port pins of PORT C
UNIT II
INTERRUPTS &
TIMER
UNIT-2 Syllabus
INTERRUPTS AND TIMER
PIC Micro Controller Interrupts

External Interrupts
Interrupt Programming
Loop Time Subroutine
Timers
Timer Programming
Front Panel I/O
Soft Keys
State Machines & Key Switches
Display Of Constant & Variable Strings
Interrupts: a review
An interrupt is any service request that
causes the CPU to stop its current
execution stream and to execute an
instruction stream that services the
interrupt
When the CPU finishes servicing the
interrupt, it returns to the original
execution stream at the point where it
left off.
Interrupt driven I/O for interfacing with
on chip peripherals
Interrupts in PIC
Sources of interrupt are many
INT pin interrupt from external source
Port B change interrupt (RB7:RB4)
Timer overflow interrupts
USART interrupts
A/D conversion interrupts
LCD interrupt
others
Interrupt Management
Use of register INTCON: Status and
Control
Bit 7: Global interrupt enable
Enables (if set) all unmasked interrupts or
disables all interrupts
Bits 6,5,4,3: For enabling peripheral, timer0,

external interrupt, port B bit change
interrupts respectively
Bits 2,1,0 : Timer0, INT, port change
interrupt flag respectively
Flag bits get set when interrupt occurs regardless
of the value of enable bit
Peripheral Interrupts
Managed using PIE and PIR
registers
PIE registers contain bits for
enabling interrupts from individual
peripherals
PIR registers contain flag bits for
individual peripheral interrupts
Bit oriented instructions can be
used to examine and/or
manipulate interrupt control and
Interrupt Processing
When interrupt is responded to
GIE bit is cleared to disable other interrupts
PC is pushed into stack
PC is loaded with 0004h
Save STATUS & W register in temporary
memory locations
In the ISR, source of interrupt is determined
by polling the interrupt flag bit
Return from interrupt instruction (retfie)

exits ISR, sets GIE bit to allow pending
interrupt to execute
Interrupt Timing
Ref: PIC reference manual
Interrupt Constraints
Each interrupt source charaterised
by
Minimum time interval between
interrupts from the same source
Maximum time it takes the CPU to
execute interrupt sources handler
Servicing of interrupts must not be

delayed beyond the limit imposed
by the timing requirement of the
source
Critical Region
A critical region is a sequence of
instructions that must be protected from
an intervening interrupt or produce
erroneous output
In PIC this problem is handled by
Single cycle read-modify-write instructions
xorwf PORTD,F
Port D data read, XORed with W and written
back to port D
Disabling interrupts by clearing GIE bit for

the required set of instructions
PIC Peripherals: Digital I/O

All PICs have digital I/O pins, called
Ports
the 8pin 12C508 has 1 Port with 4 digital I/O
pins
the 68pin 17C766 has 9 Ports with 66 digital
I/O pins
Ports used to control and monitor

external devices
Ports have 2 control registers
TRISX sets whether each pin is an input or
output
PORTX sets their output bit levels
Most pins have 25mA source/sink
Typical Configuration: Port A

Setting a
TRISA bit put
output drivers
in high
impedance
state; clearing
a bit in TRISA
puts contents
of output latch
on the pin
Example: Port A
All pins are I/O with associated direction
bits in TRISA
Initialisation code:
clrf STATUS
;bank 0
clrf PORTA
; initialises by clearing
output latches
bsf STATUS, RP0
; select bank1
movlw 0xCF
; value used to initialise data
direction
movlwf TRISA
; PortA<3:0>=input,
<5:4>=output
Managing port read/write

BCF/BSF PORTn does the following:
Reads in the PORTn byte
Clears/sets the bit
Write the whole byte back.
If external input pulls a different output pin
low or high during the READ, the read in
value will not be what you expect - WORSE,
the WRITE will permanently change it that
way.
Solution: Use Shadowed I/O (e.g.: set PORTA
Bit 0)
bsf
_PORTA, 0
movf
_PORTA, W
movwf PORTA
Synchronous Serial Port

Serial interface module for
communicating with other devices
or micro-controllers
Module operates in one of two
modes:
Serial Peripheral Interface
Inter-integrated circuit (I2C)
PIC Peripherals: Timers

Available in all PICs.
14+ bit cores may generate
interrupts on timer overflow.
Some 8 bits, some 16 bits, some
have prescalers
Can use external pins as clock
in/clock out
PIC Timers / Timer 0

8 bit timer/counter with prescaler
Readable and writeable
8-bit software programmable prescaler
Prescaler can divide the counter input by 2,4,8,16
256
Internal or external clock set

External clock connected to bit 4 of Port A
Interrupt on overflow from 0xFF to 0x00

Edge Select for external clock

16-bit timer/counter
Interrupt on overflow
Readable and writeable
Different Operating modes
External crystal can be used
Programmable prescaler
Timer1: Operating Modes

Synchronised Timer
Increments every instruction cycle
Synchronised Counter
Timer increments on rising edge of external
clock
External clock is synchronised with internal
phase clock
Asynchronous Counter
Timer increments independent of internal
phase clock
Typical
Application
: Real-time
Clock
Even when processor sleeps, timer1

continues to count in asynchronous mode,
on overflow could wake-up the device

Readable &
writable 8bit
timer/count
er with
prescaler
and
postscaler
Interrupt on
overflow
Watchdog Timer
Free running on chip RC oscillator which
does not require any external component
A WDT time-out generates a device reset
In sleep mode a WDT time-out causes the
device to wake-up
To avoid unintended device reset,
postscaler has to be changed after
clearing watchdog timer
WDT is enabled/disabled by a device
configuration bit
PIC Peripherals: CCP

Modules
Capture/Compare/PWM (CCP)
Each module contains a 16 bit register
which can operate as 16-bit capture, 16bit compare or as 10-bit PWM masterslave duty cycle register
Capture counts external pin changes
Compare will interrupt when the timer
equals the value in a compare register
Capture
Capture mode records value of
timer1 when events like rising
edge or falling edge occurs on pin
CCPx
When capture is made, interrupt
request flag bit is set
Compare
Content of register compared with
Timer1 register pair value
When match occurs, voltage level
at CCPx pin is changed depending
on the value of control bits
PWM
Pulse Width Modulation
Duty Cycle often expressed as a percentage of
the period.
Average DC voltage will be approximately the
same percentage of the on voltage.
Typical uses:
Intensity control
Motor control
Temperature control
PWM Mode
In pulse width modulation mode, CCPx
pin produces up to a 10-bit resolution
PWM output
Since CCPx pin is multiplexed with the port
data latch, the corresponding TRIS bit must
be cleared
Coupled with Timer2 for producing

output
Period and duty cycle of timer2 output
manipulated for obtaining desired PWM
waveform
PWM: Block diagram
PWM: Set up
Steps required for setting up PWM
Establish the PWM period by writing
to PR2 register
Establish the PWM duty cycle by
writing onto CCPRxL &
CCPxCON<5:4> bits
Make CCPx pin an output
Establish TMR2 prescale value and
enable timer by writing to T2CON
Configure CCP module for PWM
operation
PWM: A simple application

Speed control of a DC motor
Vary the Thigh and Tlow of the
output waveform.
When the duty ratio is changed
the speed of the Motor is
changed as average DC input
changes
PIC Peripherals: ADCs

Converts an analog input signal to 8-bit
digital value
Generates result via successive
approximation
Input analog channel, Conversion clock,

Analog reference voltage is software
selectable
Can operate even while the device in
sleep mode.
Can generate an interrupt on ADC
conversion done
Result written on to ADRES register
More PIC Peripherals

Some devices have 8-bit parallel slave
port
Multiplexed onto one of devices I/O port
For interfacing with 8-bit peripherals or
microprocessors
USART (universal synchronous and

asynchronous receiver transmitter)
Can be configured as a full duplex channel
for communication with or peripheral
devices like CRT
LCD Module
Generates timing control to drive LCD panel
Also provides control of pixel data
More PIC Peripherals

EEPROM data memory
Readable and writable under normal
operations
Not mapped directly in register file
space
Indirectly accessed using SFR
In-circuit programmer
Serial in-circuit programming support
PIC: Examples
Low End: 12C508
8pin package (DIP)
12bit core - 33 instructions
1us instruction time (Tclk = 4MHz)
512 12bit program memory
25 8bit data memory or registers (File registers)
2 level hardware stack (no interrupts)
5 GPIO pins, 1 input only (25mA source/sink)
Features: Internal pullups, wake up on pin change, internal
oscillator
Peripherals: Timer, Watch Dog Timer
PIC Examples
Mid Range: 16F876
28pin package (DIP)
14bit core - 35 instructions
200ns instruction time (Tclk = 20MHz)
8,092 14bit FLASH program memory
368 8bit data memory or registers (File registers)
256 8bit EEPROM (nonvolatile) data registers
8 level hardware stack (interrupts enabled)
22 GPIO (20mA source / 25mA 7sink)
Peripherals: 5ch 10bit ADC, USART/I2C/SPI, 16bit & 8bit
timers
Features: Brown out detect, In-Circuit Debugger (ICD)
UNIT III
PERIPHERALS
AND
INTERFACING
UNIT-3 Syllabus
PERIPHERALS AND INTERFACING
I2C Bus For Peripherals Chip Access
Bus Operation
Bus Subroutines
Serial EEPROMAnalog To Digital Converter
UART - Baud Rate Selection
Data Handling Circuit And Initialization
LCD And Keyboard Interfacing
ADC Interfacing
DAC Interfacing
Sensor Interfacing
UNIT IV
INTRODUCTION
TO ARM
PROCESSOR
UNIT-4 Syllabus
INTRODUCTION TO ARM PROCESSOR
ARM Architecture
ARM Programmers Model
ARM Development Tools
Memory Hierarchy
ARM Assembly Language Programming
Simple Examples
Architectural Support For Operating Systems
ARM
179
Introduction
Based on RISC technology

Advanced RISC Machines (ARM) was
established as a joint venture between
Acorn, Apple in 1990
ARM is leading provider of 16/ 32-bit
embedded RISC microprocessor solutions
32 bit RISC processor of load/store
architecture
180
ARM Evolution
181
ARM Evolution
From 1989-2000, 5 major version of

ARM ISA are V1 to V5
Version V1 and V2 supports
26 bit memory addressing
32 bit product multiply support
ARMv3
V3 introduced 32-bit addressing, and
architecture variants:
T Thumb state: 16-bit instruction

execution.
M long multiply support (32 32 )
These features became standard
in
182
ARMv4
Full 64 bit product multiply
instruction as well as 32 bit product
multiply instructions plus load and
store instructions (16 bit)
E.g ARM 7
ARMv5
Improved ARM and Thumb

interworking
architecture variants:
E enhanced DSP instructions including

saturated arithmetic operations and 16-bit
multiply operations
J support for new Java state. 183
ARMv6
All with T, M, E, and J extensions

More than 60 SIMD instructions
Improved Mixed-Endian Support
E.g, Little-Endian OS + Big-Endian Data
184
ARM Powered Products
185
Versions:
ARM7TDMI (3-stage)
ARMS, ARM9TDMI (5-stage)
ARM10TDMI ( 6-stage)
186
Pipeline Organization
i
n
s
t
r
u
c
ti
o
n
3-stage pipeline: Fetch Decode - Execute
Fetch
i+1
Decode
Execute
Fetch
Decode
Execute
i+2
Fetch
Decode
Execute
cycle
t+1
t+2
t+3
187t+4
Pipeline Organization
Fetch
Decode
Execute
Buffer/data
Write-back
Stages:
188
INTRODUCTION TO
PHILIPS LPC21xx
It is based on a 16/32 bit ARM7TDMI

It provides large buffer size and high processing
power.
Voltage supply 1.8V/3.3V and single supply
189
190
Device information
Device ----- LPC2138

Number of pins -----64
On-chip SRAM ------32 kB
On-chip FLASH------512 Kb
Number of 10-bit ADC
Channels
--- 16
Number of 10-bit DAC
191
ARCHITECTURE
192
Architectural overview
The ARM7TDMI-S is a general purpose 32-bit

core which offers high performance and very
low power consumption.
The ARM7TDMI-S processor has two
instruction sets
The standard 32-bit ARM set.
2) A 16-bit Thumb set.
1)
193
Interrupt
controller
The VIC accepts all of the interrupt request
inputs and categorizes them as FIQ ,
vectored IRQ, and non-vectored IRQ as
defined by programmable settings
1)Fast Interrupt request (FIQ) has the
highest priority.
2) Vectored IRQs have the middle priority.
194
Brown Out detector
The 2138 include monitoring of the

voltage on the VDD pins.
If this voltage falls below 2.9 V, the
BOD asserts an interrupt signal to
the Vectored Interrupt Controller.
195
Reset and wake-up timer
Reset has two sources on the

LPC2138: the RESET pin and
watchdog reset.
The wake-up timer ensures that

the oscillator and other analog
functions required for chip
operation are fully functional
before the processor is allowed to
execute instructions.
196
Watchdog timer
The
purpose of the watchdog is to

reset the microcontroller within a
reasonable amount of time if it
enters an erroneous state.
Crystal oscillator
On-chip integrated oscillator operates
with external crystal in range of 1
MHz to 30 MHz
197
Pulse Width Modulator (PWM)

The
PWM is based on the standard Timer
Pin description
Pin
Type
Description
PWM1
Output
Output from PWM channel 1.
PWM2
Output
PWM3
Output
Output from PWM channel 3
PWM4
Output
PWM5
Output
PWM6
Output

198
10-bit A/D
converter
Two 10-Bit Successive
Approximation ADCs, 8 channels
each
Measurement range of 0 V to 3.3
V.
199
Analog-to-Digital Converter (ADC)

Pin description
Pin
Type
Description
AD0.7:0
&
AD1.7:0
Input
Analog Inputs. The ADC cell can

measure the voltage on any of these
input signals.
VREF
Reference Voltage Reference. This pin is

provides a voltage reference level
for the A/D converter(s).
VDDA, VSSA
Power
Analog Power and Ground. These

should be nominally the same
voltages as VDD and VSS, but should
be isolated to minimize noise and
error.
200
Register description
Generic
Name
Description
Acces
s
ADCR
A/D Control Register. The ADCR register

must be written to select the operating
mode before A/D conversion can occur.
R/W
ADGDR
A/D Global Data Register. This register

contains the ADCs DONE bit and the
result of the most recent A/D conversion.
R/W
ADSTAT
A/D Status Register. This register contains RO

DONE and OVERRUN flags for all of the
A/D channels, as well as the A/D interrupt
flag.
ADGSR
A/D Global Start Register. This address

can be written to start conversions in both
A/D converters simultaneously.
201
WO
ADINTE
N
A/D Interrupt Enable Register. This register

contains
enable bits
ADDR0
A/D Channel 0 Data Register. This register

contains the result of the most recent
conversion
completed on channel 0.
ADDR1
A/D Channel 1 Data Register. This register

contains the result of the most recent
conversion
completed on channel
ADDR2,
3,
4,5,6,7
SAME DESCRIPTION
202
10-bit D/A converter
10-bit resolution DAC with a buffered

output
Based on resistor string architecture
Selectable Conversion speed vs power
Power down mode
203
Pin description
Digital-to-Analog Converter (DAC)
Pin
Type
Description
AOUT
Output
Analog Output. After the selected

settling time after the DACR is
written with a new value, the voltage
on this pin (with respect to
VSSA) is VALUE/1024 VREF.
VREF
Reference
Voltage Reference. This pin provides

a voltage reference level for
the D/A converter.
VDDA,
VSSA
Power
Analog Power and Ground. These

should be nominally the same
voltages as V3 and VSSD, but should
be isolated to minimize noise
and error.
204
DAC Register
This read/write register includes the digital value to be converted to
analog, and a bit that trades off performance vs. power. Bits 5:0 are
reserved for future, higher-resolution D/A converters.
Bit
Symb Valu Description

ol
e
5:0
15:6
Reserved, user software

should not write ones to
reserved bits. The value read
from a reserved bit is not
defined.
VALU
E
After the selected settling

time after this field is written
205
with a new VALUE,
the
16
BIAS
0
1
31:17 -
The settling time of the DAC

is 1 s max, and the
maximum current is 700 A.
The settling time of the DAC
is 2.5 s and the maximum
current is 350 A.
Reserved, user software
should not write ones to
reserved bits.
The value read from a
reserved bit is not defined.
Bits 19:18 of the PINSEL1 register (PINSEL1 - 0xE002 C004) control whether
the DAC is enabled and controlling the state of pin P0.25/AD0.4/AOUT.
206
General purpose parallel I/O

Device
pins that are not connected

to a specific peripheral function
are controlled by the GPIO
registers.
Direction control of individual bits
is set using IODIR register.
Separate control of output set and
clear.
207
Pin
connect
block
The pin connect block allows
selected pins of the
microcontroller to have more
than one function.
Configuration registers
control the multiplexers to
allow connection between the
pin and the on chip
peripherals.
208
PINSEL0 - 0xE002C000
The PINSEL0
register controls
the functions of
the pins as per the
settings listed
The direction
control bit in the
IODIR register is
effective only when
the GPIO function
is selected for a
pin.
209
210
211
212
213
General Purpose Input/Output ports (GPIO)

Pin description
Pin
Input Description
/
Outp
ut
P0.0-P.31
P1.16-P1.31
Input/
Output
General purpose input/output. The

number of GPIOs actually available
depends on the use of alternate
functions.
LPC213x has two 32-bit General Purpose I/O ports.
( 48 GPIO)
PORT1 has up to 16 pins available
for GPIO functions.
PORT0 and PORT1 are controlled via two groups of 4 registers

IOPIN, IOSET, IODIR, IOCLR
214
GPIO register map (legacy APB accessible registers)
Pin
Description
Acces
s
R/W
IOPIN
GPIO Port Pin value register. The current state of

the GPIO configured port pins can always be read
from this reg, regardless of pin direction.
IOSET
(IO0SE
T,IO1S
ET)
GPIO Port Output Set register. This register controls

the state of output pins in conjunction with the
IOCLR register. Writing 1s produces highs at the
corresponding port pins. Writing zeroes has no
effect.
R/W
IODIR
(IO0DI
R,
IO1DIR
)
GPIO Port Direction control register. This register

individually controls the direction of each port pin.
0 Input
1 output
R/W
IOCLR
(IO1CL
GPIO Port Output Clear register. This register

215
controls the state of output pin.writing 1s produces
W/O
/*SquareWave.c This program will produce a square wave of approximately 1 KHz on Pin 3 of connector JP3. It is
timed using adelay loop. */
#include <Philips\LPC2138.h>
#define CRYSTAL_FREQUENCY_IN_HZ 14745600
#define PLL_MULTIPLIER
#define DEL_LOOPS
CRYSTAL_FREQUENCY_IN_HZ*PLL_MULTIPLIER/86172
#define PIN
0x00008000
#define IODIR
IO0DIR
#define IONDIR IO1DIR

#define IOCLR
IO0CLR
#define IOSET
IO0SET
void delay()
// P0.15 = IO_A pin 1
// using P0 (IODIR: 1=out, 0=in)

// whatever port isn't used
{ unsigned i;
for (i=0; i<DEL_LOOPS; i++) {}
void main ( )
{
PINSEL0=0;
// PINSEL(0,1,2) = 0 configures pins as GPIO
PINSEL1=0;
// (probably not necessary: PINSELs default to zero)
PINSEL2=0;
// except P0.24, which doesn't exist on LPC2138
IODIR=PIN;
// only our output pin will be configured as output
IONDIR=0;
for(;;) {
IOCLR=PIN;
delay();
IOSET=PIN;
delay();
}}
216
UARTs
The LPC2138 contain two UARTs.

(UART0 and UART1)
16 byte Receive and Transmit
FIFOs.
Built-in baud rate generator.
217
UART0 & UART1

Pin description
Pin
Type
Description
RXD0
Input
Serial Input. Serial receive

data.
TXD0
Output
Serial Output. Serial transmit

data.
Register description
Name
Description
Access
U0RBR
Receiver Buffer Register
RO
U0THR
Transmit Holding Register
WO
218
I2C-bus serial I/O controller
The LPC2138 contain two I2C-bus

controllers.
The I2C-bus is bi-directional
The inter-IC control using only two
wires
1)
2)
3)
A serial clock line (SCL)

A serial data line (SDA).
The I2C-bus implemented in LPC2138
supports bit rates up to 400 kbit/s (Fast
I2C).
219
I2C interfaces I2C0 and I2C1

Pin description
Pin
Type
Descripti
on
SDA0,1
Input/Output
I2C Serial
Data.
SCL0,1
Input/Output
I2C Serial
Clock.
220
General purpose timers/external

event counters
It
consist of 2 timer
A 32-bit Timer/Counter with a
programmable 32-bit Prescaler.
221
UNIT V
ARM
ORGANIZATION
UNIT-5 Syllabus
ARM ORGANIZATION
3 - Stage Pipeline ARM Organization

5 - Stage Pipeline ARM Organization
ARM Instruction Execution
ARM Implementation
ARM Instruction Set
ARM Coprocessor Interface
Architectural Support For High Level Languages
Embedded ARM Applications
ARM Instruction
Set
227
Instruction Set
Two instruction sets:
ARM
Standard 32-bit instruction set
THUMB
16-bit compressed form
Code density better than most CISC
228
ARM Instruction Set
Features:
All instructions are 32 bits long.
Load/Store architecture
Conditional execution
Shift & ALU operation in single clock

cycle
Most instructions execute in a single cycle.
229
ARM Instruction Set
EQ
Conditional execution:
Each data processing instruction

prefixed by condition code
Result smooth flow of instructions

through pipeline
16 condition codes:
equal
NE
not equal
CS
unsigned
higher or
same
CC
unsigned
HI
unsigned
higher
positive or
zero
LS
unsigned
lower or
same
overflow
signed
GE greater than AL
or equal
MI
negative
PL
VS
VC
no overflow
LT
signed less
GT
signed
greater than
LE
signed less
than or
equal
230
NV
always
special
ARM Instruction Set

ARM instruction set
Data processing
instructions
Block transfer
instructions
Data transfer
instructions
Branching instructions
Multiply instructions
Software interrupt
instructions
231
Data Processing
Instructions
Arithmetic operations:
Bit-wise logical operations:
MOV, MVN
Comparison operations:
AND, EOR, ORR, BIC
Register movement operations:
ADD, ADC, SUB, SBC, RSB, RSC
TST, TEQ, CMP, CMN
3-address format:
Two 32-bit operands

(op1 is register, op2 is register or immediate)
Remember, this is a load / store architecture

These instruction only work on registers, NOT memory.
232
Arithmetic
Operations
Operations are:
ADD operand1 + operand2
ADC operand1 + operand2 + carry
SUB operand1 - operand2
SBC operand1 - operand2 + carry -1
RSB operand2 - operand1
RSC operand2 - operand1 + carry - 1
Syntax:
<Operation>{<cond>}{S} Rd, Rn, Operand2
Examples
ADD r0, r1, r2
SUBGT r3, r3, #1
RSBLES r4, r5, #5
Comparisons
The only effect of the comparisons is to

UPDATE THE CONDITION FLAGS. Thus no
need to set S bit.
Operations are:
CMP operand1 - operand2, but result not
written
CMN operand1 + operand2, but result not
written
TST operand1 AND operand2, but result not
written
TEQ operand1 EOR operand2, but result not
written
Syntax:
<Operation>{<cond>} Rn, Operand2
Logical Operations
Operations
are:
AND operand1
AND operand2
EOR operand1 EOR operand2
ORR operand1 OR operand2
BIC operand1 AND NOT operand2 [ie
bit clear]
Syntax:
<Operation>{<cond>}{S}
Operand2
Examples:
AND r0,
r1, r2
BICEQ r2, r3, #7
Rd, Rn,
Data Movement
Operations
are:
MOVoperand2
MVN
NOT operand2
Note that these make no use of

operand1.
Syntax:
<Operation>{<cond>}{S}
Operand2
Examples:
MOVr0,
r1
Rd,
Data Transfer
Instructions
Load/store instructions
Used to move signed and unsigned

Word, Half Word and Byte to and from
registers
LDR
Load Word
STR
Store Word
LDRH Load Half Word
STRH Store Half Word
LDRS
H
LDRB
Load Signed Half

Word
Load Byte
STRS
H
STRB
Store Signed Half

Word
Store Byte
LDRS
Load Signed Byte
STRS
Store Signed
Byte
237
Block Transfer
Instructions
Load/Store Multiple
instructions (LDM/STM)
Whole register bank or a
subset
copied to memory or
restored
with single instruction
LDM
R0
Mi
Mi+1
Mi+2
R1
R2
Mi+14
Mi+15
R14
STM
R15
238
Branching Instructions
Branch : B{<cond>} label

Branch with Link :
BL{<cond>}sub_routine_label
Branch exchange (BX) and

Branch link exchange (BLX):
239
Thumb Instruction Set
Compressed form of ARM

Instructions stored as 16-bit,
Decompressed into ARM instructions
and Executed
Lower performance (ARM 40%

faster)
Higher density (THUMB saves 30%

space)
240
THUMB Instruction Set
More traditional:
Access to R0 R8 restricted to
No condition codes
Two-address data processing instructions
MOV, ADD, CMP
Maximum 255 SWI calls
241

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EE6008

Introduction To PIC Microcontroller

PIC Architecture: Background

PIC Architecture: Background

Von Neumann & Harvard

Fetches instructions and

Limits operating bandwidth

2006 Microchip Technology Incorporated. All Rights Reserved.

Uses two separate memory

What is New in PIC?

PIC =>Peripheral Interface Controller

Low - end PIC Architectures

Mid range PIC Architectures

PIC Memory Organisation

program memory map of PIC16C74A

PIC Microcontroller Clock

Instructions : PC content no change 1

PIC 16C6x &

Port Structure and Pin Configuration

Program Counter Stack

Pipelining of instruction fetch successive

Introduction of extra cycle for a jump /

Bank - 0 and Bank -1

Register File Concept

All peripherals are

The Long Word

Register File Concept:

2006 Microchip Technology Incorporated. All Rights Reserved.

Instruction Set Overview

2006 Microchip Technology Incorporated. All Rights Reserved.

Instruction Set Overview

2006 Microchip Technology Incorporated. All Rights Reserved.

Instruction Set Overview

2006 Microchip Technology Incorporated. All Rights Reserved.

PIC16 Instruction Set

2006 Microchip Technology Incorporated. All Rights Reserved.

PIC16 Visual Interpreter

Literal Data from

2006 Microchip Technology Incorporated. All Rights Reserved.

the literal value K to register WREG and

together contents of WREG and a file

W = value in FSR register

Load k literal into WREG register

AND k literal with the content of WREG

AND the WREG register with f register

Clear bit b in file register

Instruction: BCF STATUS, 5

STATUS = 0A7H STATUS = 087H

Set bit b in f register

Instruction: BSF INTCON, 7

Execute the next instruction if bit b in file register f is

Instruction: H BTFSS STATUS, 2

Execute the next instruction if bit b in file register f is

Instruction: H BTFSC PORTA, 3

Instruction: SO CALL THEN

Instruction: CLRF PORTA

Instruction: COMP ONE, 0

Instruction: DECF CNT, 1

Decrease f register and skip the next instruction if the result is 0;

HERE DECFSZ CNT, 1

Increase the content of f register

Instruction: INCF SATU, 1

Instruction: HERE INCFSZ CNT, 1

Return with loading literal k onto WREG