AMBA AXI

Advanced eXtensible
Interface

AMBA AXI PROTOCOL

CONTENTS
Key Features
Objectives
Channel Architecture
Basic Transaction
Signal Descriptions
Addressing Options
Channel Handshake

AMBA AXI PROTOCOL

Key Features
Separate address/ control and data phases
Separate read and write channels to enable low-cost
Direct Memory Access
Burst-based transactions with only start address issued
Ability to issue multiple outstanding address
Out of order (OOO) transaction completion
Register slice support for high frequency operation

AMBA AXI PROTOCOL

Objectives
Be suitable for high-bandwidth and low-latency
designs
Enable high-frequency operation
Fit for devices with high initial latency
Provide flexibility of interconnect architectures
Be backward-compatible with existing AHB and
APB interfaces.

AMBA AXI PROTOCOL

Channel Architectures

Five unidirectional channels

AMBA AXI PROTOCOL

AXI Burst Start Address for a Burst

Reduce the address channel utilization

Use Address/ Control channel more efficiently
Pipeline

AMBA AXI PROTOCOL

Outstanding Transactions

Decouple the fixed link between address and data

Enable parallel processing of transactions

AMBA AXI PROTOCOL

Out Of Order (OOO) completion

Fast Slave may return data before slow slaves

Complex slaves may return data out of order
Effectively reduce the transaction latency

AMBA AXI PROTOCOL

Data Interleaving

Data within a burst is always in order

Each transaction has a unique ID

AMBA AXI PROTOCOL

Register slices support for high frequency operation ?
Allows maximum frequency of
operation by matching channel
latency to channel delay

AMBA AXI PROTOCOL

Channel Handshake

VALID READY two way handshaking

- sources generate VALID to indicate when the data is
valid
- destinations generate READY to indicate when the data
is accepted
Successful tranfer must qualify both VALID and
READY
No combination paths between masters and slaves
- All timing paths must be registered

AMBA AXI PROTOCOL

Channel Handshake
Handshaking Timing Diagram
1.VALID before READY handshake.
When the destinations drives the
READY signal high, indicating that it
accepts the data or control information
2.READY before VALID handshake.
This indicates that the destination can
accept the data or control information in a
single cycle

3.READY with VALID handshake.

Both the source and destination happen
to indicate in the same cycle

AMBA AXI PROTOCOL

Channel Handshake
Two way handshaking typically needs 2-cycles
- 1st cycle for VALID high and 2nd cycle for READY
If a slave can always accept any valid address, the default value of READY will
be HIGH, although if READY is HIGH then the slave must be able to accept
any valid address that is presented to it.
If the default READY value of LOW, it can take at least two cycle, but one
cycle is ok. So why the default READY value need HIGH ?
If the master can always accept any valid data, READY will be always HIGH
for 1-cycle handshaking

AMBA AXI PROTOCOL

Channel Handshake
Dependency in Read Transactions
A slave can wait for ARVALID before asserting ARREADY
A slave must wait for ARVALID & ARREADY before
asserting RVALID
A master can wait for RVALID before asserting RREADY

AMBA AXI PROTOCOL

Channel Handshake
Dependency in Write Transactions
A slave can wait for AWVALID, WVALID or both before asserting
AWREADY
A slave can wait for AWVALID, WVALID or both before asserting
WREADY
A slave must wait for WVALID & WREADY before asserting BVALID
A master can wait for BVALID before asserting BREADY
IMPORTANT NOTE :
Master must not wait for
AWREADY to be asserted before
driving WVALID. This could cause a
deadlock condition if the slave is
conversely waitting for WVALID
before asserting AWREADY

AMBA AXI PROTOCOL

Basic Transactions
Read Burst Example

4-beat read burst

AMBA AXI PROTOCOL

Basic Transactions
Overlapping Read Burst Example

3-beat read burst + 2-beat read burst

AMBA AXI PROTOCOL

Basic Transactions
Write Burst Example

4-beat write burst

AMBA AXI PROTOCOL

Signals Descriptions
Signals of Write Address Channel

AMBA AXI PROTOCOL

Signals Descriptions
Signals of Write Data Channel

AMBA AXI PROTOCOL

Signals Descriptions
Signals of Write Response Channel

AMBA AXI PROTOCOL

Signals Descriptions
Signals of Read Address Channel

AMBA AXI PROTOCOL

Signals Descriptions
Signals of Read Data Channel

AMBA AXI PROTOCOL

Addressing Options
Master provide the start address of the burst
Slave are in charge to calculate the address of subsequent
transfers in a burst
Burst can not across 4KB boundary
- Address is allocated to a slave in 4KB unit

AMBA AXI PROTOCOL

Addressing Options
Burst Length
Burst length specifies the number of data
tranfers that occur within each a burst.
For wrapping burst, the length of the burst
must be 2, 4, 8 or 16 tranfers.

AMBA AXI PROTOCOL

Addressing Options
Burst Size
Burst size specifies the maximum number of
data bytes to transfer in each beat, within a
burst.
For incrementing and wrapping bursts and
transfer sizes are smaller than the data bus
width
- Transfers are on different byte lanes for
each burst ( driving by write strobe)
For fixed bursts
- Address remains constant within a burst
- Every transfer use the same byte lane

AMBA AXI PROTOCOL

Addressing Options
Burst Type

Fixed burst
- Address remains the same for every transfer in the burst
- Repeat access to the same location
Incrementing burst
- Address for the each transfer in the burst is an increment of the previous address
- The increment value depends on the size of the transfer
Wrapping burst
- The start address must be aligned to the size of the transfer
- The length of the burst must be 2, 4, 8 or 16.

AMBA AXI PROTOCOL

Addressing Options
Burst Address
Start Address : the start address issued by the master
Number bytes : the maximum number of bytes in each data
transfer
Data_bus_bytes : the number of byte lanes in the data bus
Aligned_address : the aligned version of the start address
Burst_length : the total number of data transfers within a burst
Address_N : the address of transfer N within a burst. N is an
integer from 2-16
Wrap_boundary : the lowest address within a wrapping burst
INT(x) : the rounded-down integer value x

AMBA AXI PROTOCOL

Addressing Options
Burst Address - formulas
Start Address = ADDR
Number_bytes = 2^SIZE
Burst_length = LEN + 1
Aligned_address = (INT(Start_address / Number_Bytes)) x Number_Bytes
Address1 = Start_Address
Address_N = Aligned_address + (N-1) x Number_Bytes
For wrapping burst, the wrap_boundary variable is extended to account for the
wrapping boundary :
Wrap_boundary = (INT(Start_address / (Number_Bytes x Burst_length))) x
(Number_Bytes x Burst_length)
If Address_N = wrap_boundary + (Number_Bytes x Burst_length), use this equation
Address_N = Wrap_boundary.

AMBA AXI PROTOCOL

Addressing Options
Example Wrapping Address

Start_Address = 0x4a ; Burst_size = 3b010;

Number_Bytes = 2^SIZE = 2^2 = 4
Burst_length = 4
Aligned_address = (INT(Start_address / Number_Bytes)) x Number_Bytes
= (INT( 0x4a / 4) x 4
= 0x48

Address_1 = Start_address = 0x4a

Address_2 = Aligned_address + (N-1) x Number_Bytes
= 0x48 + (2-1) x 4
= 0x4c
Address_3 = 0x48 + (3-1) x 4
= 0x50
Wrap_boundary = (INT(Start_address / (Number_bytes x Burst_length))) x
(Number_bytes x Burst_length)
= (INT( 0x4a / (4x4)) x (4x4)
= 0x40

AMBA AXI PROTOCOL

Addressing Options
Example Wrapping Address
Address_3 = Wrap_Boundary + (Number_Bytes x Burst_length)
= 0x40 + (4 x 4)
= 0x50
Address_3 = Wrap_boundary = 0x40
Address_4 = 0x44

Start_address

0x4b

0x4a

0x49

0x48

1st transfer

0x4f

0x4e

0x4d

0x4c

2st transfer

0x43

0x42

0x41

0x40

3st transfer

0x47

0x46

0x45

0x44

4st transfer

Write Strobes
WSTRB : Write strobes. This signal indicates which byte lanes to update in memory.
There is one strobe for each eight bits of the write data bus.
WDATA : 8 1024 bits wide
WSTRB : 1 128 bits wide

64-bit write data bus

63

WSTRB

56 55

48 47

40 39

32 31

24 23

16 15

Aligned Transfer
Address: 0x00
Transfer size: 32 bits
Burst type: incrementing
Burst length: 4 transfers

For wrapping burst type, all

transfers are aligned transfers

64-bit write data bus

63

WSTRB

WSTRB

56 55

48 47

40 39

32 31

24 23

16 15

F
7

E
6

D
5

C
4

B
3

A
2

1
9

0
8

Unaligned Transfer
Address: 0x07
Transfer size: 32 bits
Burst type: incrementing
Burst length: 4 transfers

For incrementing burst type, fist

transfer can be unaligned
transfers, but the rest transfers are
aligned transfers

64-bit write data bus

63

WSTRB

WSTRB

56 55

48 47

40 39

32 31

24 23

16 15

F
7

E
6

D
5

C
4

B
3

A
2

1
9

0
8

F
7

E
6

D
5

C
4

B
3

A
2

1
9

0
8

17

16

15

14

13

12

11

10

Cache Support
Support for system level caches and other performance
enhancing components
Bufferable (B) bit, ARCACHE[0] and AWCACHE[0]
Cacheable (C) bit, ARCACHE[1] and AWCACHE[1]
Read Allocate (RA) bit, ARCACHE[2] and AWCACHE[2]
Write Allocate (WA) bit, ARCACHE[3] and AWCACHE[3]

Bufferable Bit
The interconnect or any component can delay the transaction
for an arbitrary number of cycles, usually only relevant to
writes
1
A1

1 1 1
A1 A2 A3

AXI
Master2

1
A3

2 2 2 2 2 2
B1 B1 B2 B2 B3 B3

AXI
Master1
2 2 2
B1 B2 B3

1
A2

AXI
Interconnect

1 2 1 2 1 2
A1 B1 A2 B2 A3 B3

AXI
Slave1
Write interleaving
depth = 2

Bufferable Bit (Conti.)

IF a transaction is bufferable
It is acceptable for a bridge or system level cache to provide write
response

If non-bufferable
Final destination to provide response

Bufferable
AXI
Master1

Non-bufferable
AXI
Interconnect

AXI
Master2

AXI
Slave1

Cache Support
Cacheable Bit
Write : a number of different writes can be merged together
Read : a location can be pre-fetched or can be fetched just once for
multiple read transactions

Read Allocate Bit

If the transfer is a read and it misses in the cache then it should be
allocated

Write Allocate Bit

If the transfer is a write and it misses in the cache then it should be
allocated

Cacheable Write Sparse Strobes

Cacheable Bit
Write : a number of different writes can be merged together
ARM11-MPCore processor and L220 Level 2 cache controller use sparse strobes. This is due to the
fact that they use a merging write buffer. If the application writes several bytes at address 0x0, 0x3,
0x4, the write buffer will be drained using a 64-bit transfer, and strobes will be 0b00011001 and
the AXI slave must only update the bytes that are enabled.
64-bit write data bus
63

WSTRB

56 55

48 47

40 39

32 31

24 23

16 15

Cache Encoding

ARCACHE[3:0]
AWCACHE[3:0]

C : low
RA : low
WA : low

Protection Unit Support

To support complex system design, for the interconnect and
other devices in the system to provide protection against illegal
transactions
Normal or privileged, ARPROT[0] and AWPROT[0]
Low
High
Secure or non-secure, ARPROT[1] and AWPROT[1]
High
Low
Data or instruction, ARPROT[2] and AWPROT[2]
Low
High

Normal / Privileged
This is used by some masters to indicate their processing
mode. A privileged processing mode typically has a greater
lever of access within a system
AXI
Master1

CPU

AXI
Master2

Normal
access
AXI
Slave1
Privileged
access

Normal
access

AXI
Interconnect
AXI
Slave2

Secure / Non-secure
This is used in systems where a greater degree of
differentiation between processing modes is required
Non-secure

AXI
Slave1
(Secure)

Secure

AXI
Master1

AXI
Interconnect

AXI
Slave2
(Non-secure)

AXI
Slave3
(Non-secure)

SLVERR response
OKAY response
DECERR response
Non-secure slave
disappears from the
memory map during
secure accesses

Data / Instruction
This bit gives an indication if the transaction is an instruction
or a data access
When a transaction contains a mix of
instruction and data items
Its recommended that, by default, an access
is marked as a data access unless specifically
known to be an instruction access

Instruction

Data

Data

Access / Response Signals

Access Signals

Response Signals

Slave-generated errors
Address decode errors

Exclusive Access
Master1
Exclusive Read

Semaphore type without

locking the bus access
Exclusive Read success
Response : EXOKAY

Cycle 1

2 3

2 3

Master2
Write

Exclusive Read fail

Response : OKAY

Cycle 2
Master1
Exclusive Write

Exclusive Write success

Response : EXOKAY

Cycle 3

2 3

Exclusive Write fail

Response : OKAY

Advantages of AXI Protocol

Independently acknowledged address and data channels
Out-of-order completion of bursts
Write data interleaving
Exclusive access (atomic transaction)
Access security support
System level cache support
Unaligned address & byte strobe
Static burst, which allows bursts to FIFO memory
Low power mode