PROGRAMMABLE

PERIPHERAL INTERFACING

Introduction to 8255 PPI

The Intel 8255A is a high-performance,

general purpose programmable I/O
device

is designed for use with all Intel and most

other microprocessors

It provides 24 I/O pins

Can be individually programmed in 2

groups of 12
Used in 3 major modes of operation
Each group of 12 I/O pins may be
programmed in sets of 4 and 8 to be inputs

Contd

In MODE 0, each group of 12 I/O pins

may be programmed in sets of 4 and 8
to be inputs or outputs
In MODE 1, each group may be
programmed to have 8 lines of input or
output.

3 of the remaining 4 pins are used for

handshaking and interrupt control signals.

MODE 2 is a bi-directional bus

configuration.

8255A BLOCK DIAGRAM AND FUNCTIONAL DESCRIPTION

Contd

Data Bus Buffer

This 3-state bidirectional 8-bit buffer is used to

interface the 8255A to the system data bus
Data is transmitted or received by the buffer upon
execution of input or output instructions by the CPU
Control words and status information are also
transferred through the data bus buffer

Read/Write and Control Logic

manage all of the internal and external transfers of

both Data and Control or Status words.
It accepts inputs from the CPU Address and Control
busses and in turn, issues commands to both of the
Control Groups.

Contd

Group A and Group B Controls

CPU outputs a control word to the 8255A

The control word contains information such as
mode, bit set, bit reset, etc
Each of the Control blocks (Group A and Group B)
accepts

``commands'' from the Read/Write Control

Logic,
receives ``control words'' from the internal data bus
issues the proper commands to its associated ports

Control Group A - Port A and Port C upper (C7-C4)

Control Group B - Port B and Port C lower (C3-C0)

Ports A, B, and C

The 8255A contains three 8-bit ports (A, B, and C)

All can be configured in a wide variety of
functional characteristics
each has its own special features or personality
to further enhances the power and flexibility of
the 8255A

Port A: One 8-bit data output latch/buffer and one 8bit input latch buffer
Port B: One 8-bit data input/output latch/buffer
Port C: One 8-bit data output latch/buffer and one 8bit data input buffer (no latch for input)
This

port can be divided into two 4-bit ports under the

mode control

8255A OPERATIONAL DESCRIPTION

There are three basic modes of operation that can

be selected by software:

Mode 0 Basic input/output

Mode 1 Strobed Input/output
Mode 2 Bi-directional Bus

When the reset input goes ``high'' all ports will be

set to the input mode

After the reset is removed the 8255A can remain in the

input mode with no additional initialization required
During the execution of user program
the

other modes may be selected by using a single output

instruction.
This allows a single 8255A to service a variety of peripheral
devices with a simple software maintenance routine

Contd

The modes for Port A and Port B can be

separately defined, while Port C is
divided into two portions as required by
the Port A and Port B definitions
Modes may be combined so that their
functional definition can be suited to
almost any I/O structure
For instance

Group B can be programmed in Mode 0 to

monitor simple switch closings or display
computational results,
Group A could be programmed in Mode 1 to

Bit Set/Reset, Control word and control register

BSR
In this mode, individual bits of port C can be used for
applications such as on On/Off switch.
Any of the eight bits of Port C can be Set or Reset using a
single Output instruction
This feature reduces software requirements in Controlbased applications
CONTROL WORD: control word format for I/O mode is
shown in fig below. It is essential to understand this
format.
In interfacing applications

we have to determine the control word for programming the

ports for input or output and write it into the
CONTROLREGISTER before the data transfer program
This way of determining and writing the CONTROL WORD is
called I/O programming

Contd

To communicate with periphera1s

through 8255A, three steps are
necessary

Determine the addresses of ports & control

register from the chip select logic.
Write a control word into the
contro1register.
Write instructions to transfer data to the
peripherals through ports A, B & C

Mode 0: Simple Input or

Output
Ports A, B &C are programmed for simple
I/O.
Outputs are latched.
Inputs are -not latched.
Ports do not have handshake or interrupt
capability.
Example: -twelve DIP switches are
interfaced to 8085A via port B and port
CL. Twelve LEDs are interfaced via port A
and port CL as shown below

Identify the port addresses.

Determine the control word to configure port A-&
port Cu for output and port B and port C L or input.
Write a program to read the DIP switches from
port B and port CL and to display the readings at
port A and port Cu respectively

From the circuit, observe-that the control-signals MEMR and MEMW are connected

This indicates to us that the devices-are interfaced

in MEMORY MAPPED MODE
So, they will have 16-bit addresses. CS is
connected to Al5 through an inverter. So A15 must
be at logic high level for the 8255A to be selected.

Mode 1 Input/Output with Handshake

In mode 0, which is used for simple I/O, it is

assumed that the peripheral devices are always
ready
The microprocessor, therefore, need not to check
their status before transferring data to and from
However this is not the case always

Sometimes in order to check the-status, the Mp and

the peripherals exchange a few signals prior to
actual data transfer
These signals are called hand shake signals
The 8255A's capability to transfer data with
handshake is provided in its mode 1 operation

Contd

Feature of Mode 1:

Port A and port B function as 8-bit I/O ports.

Each port uses three bits from port C as
handshake signals. The remaining two bits
from port C can be used for simple I/O.
Input-data and output data are latched.
Interrupt logic is supported.