THE AGING-AWARE VEDIC

MULTIPLIER DESIGN WITH THE AHL

Abstract
The multiplier is able to adjust the
AHL to mitigate performance
degradation due to increased delay.
The negative bias temperature
instability occurs when a PMOS
transistor is under negative bias. In
the interaction between inversion
layer holes and hydrogen-passivity Si
are atoms breaks.

Contin..
DIGITAL multipliers are among the
most critical arithmetic functional
units in many applications, such as
the Fourier transform, discrete cosine
transforms, and digital filtering. The
throughput of these applications
depends on multipliers, and if the
multipliers are too slow, the
performance of entire circuits will be
reduced.

Existing system
Digital multipliers are among the most critical arithmetic
functional units.
Overall performance of the VLSI system is mainly depends on
the multiplier
The speed of the multipliers is affected by NBTI and PBTI.
NBTI effect occurs when, a PMOS transistor is under negative
bias (vgs = -vdd), which will increase the threshold voltage of
PMOS transistor.
Similarly, PBTI effect occurs when an NMOS transistor is
under positive bias.
There is no improvements in aging effect performance
degradation is more time waste.

Variable-Latency Design
The basic concept is to execute a
shorter path using a shorter cycle
and longer path using two cycles.
Since most paths execute in a cycle
period that is much smaller than the
critical path delay, the variablelatency design has smaller average
latency.

Proposed system
Vedic multiplier is that here partial
product generation and additions are done
concurrently. Hence, it is well adapted to
parallel processing.
The feature makes it more attractive for
binary multiplications. This in turn reduces
delay.
the least significant bits are multiplied
which gives the least significant bit of the
final product (vertical).

Vedic multiplier
The use of Vedic mathematics is to reduces the typical
calculations in conventional mathematics to very simple
one. Because the Vedic formulae are claimed to be based
on the natural principles on which the human mind works.
Vedic Mathematics is a methodology of arithmetic rules
that allow more efficient speed implementation.
It is a general multiplication formula applicable to all cases
of

multiplication.

Crosswise.

It

literally

means

Vertically

and

2x2 vedic multiplier

AHL with multiplier

Adaptive hold logic

The key component in variablelatency multiplier is the AHL circuit.
The AHL circuit contains an aging
indicator, two judging blocks, one
multiplexer, and one D flip-flop.
The aging indicator indicates
whether the circuit has suffered
significant performance degradation
due to the aging effect.

Adaptive hold logic

ADVANTAGES
Solves long discharging path
problem.
Has the smallest layout area.
The proposed design is the most
efficient.

APPLICATIONS
Memory devices
Low power circuits
Future mobile ICs.

Reference
Y. Cao. (2013). Predictive Technology Model (PTM) and NBTI
Model [Online]. Available: http://www.eas.asu.edu/ptm
S. Zafar et al., A comparative study of NBTI and PBTI (charge
trapping) in SiO2/HfO2 stacks with FUSI, TiN, Re gates, in
Proc.IEEE Symp. VLSI Technol. Dig. Tech. Papers, 2006, pp. 2325
S. Zafar, A. Kumar, E. Gusev, and E. Cartier, Threshold voltage
instabilities in high-k gate dielectric stacks, IEEE Trans. Device
Mater.Rel., vol. 5, no. 1, pp. 4564, Mar. 2005
H.-I. Yang, S.-C. Yang, W. Hwang, and C.-T. Chuang, Impacts of
NBTI/PBTI on timing control circuits and degradation tolerant
design
in nanoscale CMOS SRAM, IEEE Trans. Circuit Syst., vol. 58, no.
6,
pp. 12391251, Jun. 2011