Lesson 2:

Topic:
A. General FPGA Programming Techniques

Agenda
FPGA Palette
Basic FPGA VI
Parallelism and Shared Resources
Integer Math Issues

FPGA Palette
FPGA specific functions
Programming structures
Device I/O
Arithmetic and Boolean Logic
Arrays and clusters
Timing
Math and control functions
Synchronization and FIFOs
Lookup tables

Basic FPGA VI
F=(A+B)CD

LabVIEW Mapped to FPGA

Implementing Logic on FPGA: F =(A+B)CD
F

A
B
C
D

Compile Process and Server

Convert LV diagram to intermediate files
Send intermediate files to the compile server
Compiles VIs for FPGA
Returns FPGA bitstream to LabVIEW
Bitstream is stored in VI

LabVIEW environment is a client

Compile
Server

Can disconnect from server and reconnect while compiling

Download
Windows OS
LabVIEW FPGA Module

Occurs automatically
after a compile
initiated by the run
button

FPGA VI
Bit File Embedded

Target FPGA
Download

FPGA VI (actually
the bit file)

Interactive Mode
Windows OS
LabVIEW FPGA Module

Interact with VI on FPGA

through Front Panel
No Debugging
VI is running in the FPGA
Target FPGA

FPGA VI
(Front Panel)
Updates

FPGA VI
(running)

Host PC Interactive Mode

Windows OS

Interact with FPGA through

host PC based Front Panel
Allows you to do other
processing in Host VI
Target FPGA

VI
(Front Panel)
Updates

FPGA VI
(running)

Windows Target Mode

Windows OS
LabVIEW FPGA Module
(targeted to Windows)

Run FPGA VI on Windows

Software Emulation
No hardware timing

Debugging possible
FPGA VI

Check logic before compile

Exercise 2.1
Create a VI which adds two
numbers and runs a
benchmark in parallel that
determines how fast code is
running
exercise_2.1.doc

Open the Spartan 3E

example and build the
program
Exercise_2.1Getting Started Spartan 3E.doc

Shared Resources
Before a task can begin using a shared resource, it must wait until it
is free.
Task 1

Shared

Task 2

Resource
Running

Waiting

After Task 1 finishes, Task 2 can proceed.

Task 1

Shared

Task 2

Resource
Waiting

Running

Sharing Resources
Shared Resources:
Digital Outputs
Memory/FIFOs
Non-Reentrant VIs
Local Variables

Shared Resources Example

Sharing VIs (non-Reentrant VIs)

Non-Reentrant (Default)
The VI is shared
Only one instance on the FPGA device

Reentrant VI
Separate set of gates on the FPGA device for each instance
on the diagram (uses more space)
Configure by Right-Clinking on Resource and selecting Properties

Integer Math

No floating point
Singles and doubles type
are not supported

Integer Math
Scaling of data required for analysis and output operations
Replaces floating point multiplication/division on the FPGA
Most useful for 16-bit integers, use 32-bit width during calculation

Operations
Multiply value by integer scaling factor
Scale result by a predetermined power of 2
Combined effect provides non-integer multiplication

Integer Math
For variable scaling, you can determine and set the scaling
factor and bit shift from the host application

For example: Scaling Factor: 11500

Downshift: -14 bits
Result Multiplication: 11500 / 16384 = 0.7019

Integer Math
Saturation Arithmetic VIs
used to handle or avoid
integer overflow when
performing mathematical
operations
Two types of results when
overflow
-Saturate
-Wrap

Other Examples to Learn More

\FPGA Fundamentals- in the examples folder