COMBINATIONAL CIRCUITS

&
SEQUENTIAL CIRCUITS
 COMBINATIONAL
CIRCUITS
1. Selected Signal Assignment:
. Used to assign signal one of several values.
Syntax: with expression select
signal name <= expression when
constant_value;
Example: Write VHDL code for mux 2:1
using selected signal assignment.
Example: Write VHDL code for mux 4:1
using selected signal assignment.
Example: Write VHDL code for mux 16:1 using package in structural style.
Example: Write VHDL code for 2:4 binary
decoder using selected signal assignment .
2. Conditional signal assignment:
. Similar as selected signal assignment operator
(but uses when and else),
. And it also uses conditional signal assignment
operator i.e.
=.
Example: Write VHDL code for mux 2:1 using
conditional signal assignment.
Example: Write VHDL code for 4:2 priority
encoder using conditional signal assignment.
Example: Write VHDL code for 4-bit comparator
using conditional signal assignment (including
std_logic_unsigned library).
Alternate code for 4-bit comparator
3. Generate Statement:
. It is a feature that describe regularly structural
hierarchical code using loop and reduce coding.
Syntax 1:
generate_label: for index_variable in range
generate
statement;
end generate;

Syntax 2:
generate_label: if expression generate
statement;
end generate;
Example: Write VHDL code for mux 16:1 using
generate statement.
Example: Write VHDL code for decoder 4:16
using generate statement.
4. Process statement:
Example: Write VHDL code for mux 2:1 using process
statement.
5. Case statement:
Similar to selected signal assignment but in this for selected signal WHEN
clause is used for its various values.

Example: Write VHDL code for decoder 2:4 using case statement.
Example: Write VHDL code for BCD to 7-
segment decoder using case statement.
 SEQUENTIAL CIRCUITS
Output depend on both present and past input.
Hence have some storage and therefore States exist in it.
Combinational circuits are known as memoryless or
stateless.
Comparison between combinational and
sequential circuits.
Types of Sequential circuits:
1. Synchronous, and
2. Asynchronous circuits.

Comparison between synchronous and asynchronous circuit.

Basic bi-stable element
Use for set and reset but latch in that state only till
external source is applied and does not have
memory.
Modified SR Latch

Two extra nand gates are used for memory.

Drawback: Sensitive to input all the time.
Truth Table

S R Q
0 0 Q
0 1 0
1 0 1
1 1 Indet
.
Gated SR Latch
To make it less sensitive to input and enable is added so
that it will be sensitive to input only when enable is 1.

Truth Table

En S R Q
1 0 0 Q
1 0 1 0
1 1 0 1
1 1 1 Indet
.
0 X X Q
Example: Write VHDL code for gated D latch.
Clocked SR Flip Flop
Used to set and reset output.
State is changed using clock cycle.
Drawback: Indetermined condition when both
input are 1.
Solution: D or JK Flip Flop.
Truth Table

clk S R Q
PE 0 0 Q
PE 0 1 0
PE 1 0 1
PE 1 1 Indet
.
0 X X Q
D (Delay) Flip Flop
Also known as transparent flip flop.
Indet. Condition will never arrive as both input
will never be 1.

Truth Table

D Q
0 0
1 1
 Example: Write VHDL code for clocked D flip flop
using Clockevent (it means the clock has
changed just now and it is equal to 1 for
positive edge triggering).
Example: Write VHDL code for clocked D flip flop using WAIT UNTIL
statement (wait until work same as if statement in previous example and
also sensitivity list is omitted in process statement)
Example: Write VHDL code for D flip flop with
asynchronous reset
Example: Write VHDL code for D flip flop with
synchronous reset
JK Flip Flop
It eliminate indet. Condition of SR flip flop by
making S = J. and R = K.Q
Drawback: Output toggle when both input are 1.
Solution: JK Master-Slave flip flop or T-flip flop.

Truth Table

J K Q
0 0 Q
0 1 0
1 0 1
1 1
JK Master- Slave flip flop
Problem: Race around condition which arrives when
output changing time t is less than clock pulse tp.
Solution: either t > tp or use master-slave flip flop.
Master: Positive edge triggered.
Slave : Negative edge triggered (i.e. Slave copies
master at negative edge).
T(Toggle)-flip flop
It is modified version of JK flip flop.
Toggle condition will never arrive as single input
is given to both the nand gates.

Truth Table

T Q
0 Q
1
D flip flop with CLEAR and PRESET for
Counters
Sequential circuits depend on both past and
present input of the circuit.
Counter either has to increment (UP counter) or
decrement (DOWN counter).
So it is required to clear all the flip flop i.e. its
initial state if Q=0 or preset if Q=1 for
counting.
So on the basis of clock pulse, counters are of two
types:
1. Asynchronous counter.
2. Synchronous counter.
1. Asynchronous Counter with Preset and Clear

When output become 0 on clear 0 immediately

regardless of clk.
In this both clear and preset are active low, so it will work
when preset and clear is 0 and not on 1.
When clear=0, then Q (output)=0.
When clear=1, then Q = has no effect on output.
When preset=0, then Q = 1.
When preset = 1, then Q = has no effect on output.
Preset and clear will never be 0 simultaneously.
2. Synchronous Counter with Preset and Clear

When output become 0 on clear 1 only on

active edge of clock.
In this both clear and preset are active high,
so it will work when preset and clear is 1 and
not on 0.
When clear=1, then Q (output)=0.
When clear=0, then Q = has no effect on
output.
When preset=1, then Q = 1.
When preset = 0, then Q = has no effect on
output.
Registers
Flip flop store one-bit of info, so group of flip flop is
known as register.
Types of registers:
1. Shift register.
2. Parallel access shift register.

Shift Register:
. A no. is multiplied by 2 if its one-bit is shifted to left
and 0 is inserted at new LSB.
. A no. is divided by 2 if its one-bit is shifted to right
and 0 is inserted at new MSB.
. A register that provide ability to shift its contents is
known as Shift register.
A simple shift register, input sequence=10111000
Example: Write VHDL code for 4-bit shift
register
Example: Write VHDL code for 8-bit register
with asynchronous clear
Example: Write VHDL code for n-bit register
with asynchronous clear
 Types of shift register:
1. Serial In Serial Out (SISO).
2. Serial In Parallel Out (SIPO).
3. Parallel In Serial Out (PISO).
4. Parallel In Parallel Out (PIPO).

Parallel access shift register:

. If we want to transfer n bit through single wire,
is known as serial transfer.
. If we want to transfer n bit through n separate
wire, is known as parallel transfer.
. Both operations can be performed using parallel
access shift register.
 In one clock cycle, n bits are parallely loaded and in
next n clock cycle the data are shifted for serial
output (when output is taken at Q0).
Similarly, in one clock cycle, n bits are serially
loaded and in next n clock cycle the data are
shifted for parallel output (when output is taken at
Q0, Q1, Q2 and Q3).
Here input of D f/f is connected with two different
sources:
I source: preceding f/f for shift operation.
II source: external input for parallel load operation.
Shift / Load

i.e. if Shift / Load = 0, then shift mode of operation

will work.
And if = 1, then parallel data load
operation will work.
Example: 4-bit parallel access shift register
Library ieee;
Use ieee.std_logic_1164.all;
Entity shift4 is
Port(p: in std_logic_vector(3 downto 0);
s,l,clk: in std_logic;
q: out std_logic);
End shift4;
Architecture structure of shift4 is
Component muxdff
Port(d0,d1,set,clock: in std_logic;
q:out std_logic);
End component;
Begin
Stage3: muxdff port map (p(3),s,l,clk,q(3));
Stage2: muxdff port map (p(2),q(3),l,clk,q(2));
Stage1: muxdff port map (p(1),q(2)l,clk,q(1));
Stage0: muxdff port map (p(0),q(1),l,clk,q(0));
End structure;
Counters
Types of counters:
1. Asynchronous /ripple/serial counter.
2. Synchronous/parallel counter.

Asynchronous counter:
. Clock is given to only I flip flop and then output
of preceding flip flop will work as clock for next
flip flop.

Types of asynchronous counter are:

1. Up counter.
2. Down counter.
Up counter
Example: A three bit up-counter using T flip
flop.

Here Q0 depend on clock hence change when

clock goes from 0 to 1 or at positive clock edge.
Q1 and Q2 depends upon 0 and 1 resp. hence
changes when they goes from 1 to 0 or at negative
edge.
Q2 Q1 Q0 Clk
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7
0 0 0 8

Total no. of clock cycle required to count from 000

to 111 = 7 (0 to 7).
Hence it is Mod-7 counter.
No. of f/f required for Mod-7counter = log27 = 3 f/f
Example: Write VHDL code for 4-bit up counter
Down counter
Example: A three bit down-counter using T flip
flop.

Here Q0 depend on clock hence change when

clock goes from 0 to 1 or at positive clock edge.
Q1 and Q2 depends upon Q0 and Q1 resp. hence
changes when they goes from 0 to 1 or at positive
edge.
Q2 Q1 Q0 Clk
1 1 1 0
1 1 0 1
1 0 1 2
1 0 0 3
0 1 1 4
0 1 0 5
0 0 1 6
0 0 0 7
1 1 1 8

Total no. of clock cycle required to count from 111

to 000 = 7 (0 to 7).
Hence it is Mod-7 counter.
No. of f/f required for Mod-7 counter = log27 = 3 f/f
Synchronous counter:
Here in this clock is given to individual f/f hence
output has to wait for next clock pulse.

Types of synchronous counter are:

1. Up counter.
2. Down counter.

Example: Three bit synchronous up counter

using T flip flop.
Q2 Q1 Q0 Clk
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7
0 0 0 8

Total no. of clock cycle required to count from 000

to 000 = 8 (0 to 8).
Hence it is Mod-8 counter.
No. of f/f required for Mod-9 counter = log28 = 3 f/f
Equations
T0 = 1
T1= Q0
T2 = Q0 Q1
.
.
.
Tn = Q0 Q1............Qn-1
Example: Four bit synchronous up counter
using T flip flop.
 Assignment

Study other types of counters such

as BCD counter, Ring counter and
Johnson counter.