Chapter 5

Computer System Architectures

Based on
Digital Design and Computer Architecture,
2nd Edition
David Money Harris and Sarah L. Harris

Chapter 5 <1>
 Introduction
Digital building blocks:
Gates, multiplexers, decoders, registers,
arithmetic circuits, counters, memory arrays,
logic arrays
Building blocks demonstrate
hierarchy, modularity, and regularity:
Hierarchy of simpler components
Well-defined interfaces and functions
Regular structure easily extends to different
sizes

Chapter 5 <2>
1-Bit Adders
Half Full
Adder Adder
A B A B

Cout Cout Cin

+ +
S S

A B Cout S Cin A B Cout S

0 0 0 0 0
0 1 0 0 1
1 0 0 1 0
1 1 0 1 1
1 0 0
S = 1 0 1
Cout = 1 1 0
1 1 1

S =
Cout =

Chapter 5 <3>
1-Bit Adders
Half Full
Adder Adder
A B A B

Cout Cout Cin

+ +
S S

A B Cout S Cin A B Cout S

0 0 0 0 0 0 0 0 0
0 1 0 1 0 0 1 0 1
1 0 0 1 0 1 0 0 1
1 1 1 0 0 1 1 1 0
1 0 0 0 1
S = 1 0 1 1 0
Cout = 1 1 0 1 0
1 1 1 1 1

S =
Cout =

Chapter 5 <4>
1-Bit Adders
Half Full
Adder Adder
A B A B

Cout Cout Cin

+ +
S S

A B Cout S Cin A B Cout S

0 0 0 0 0 0 0 0 0
0 1 0 1 0 0 1 0 1
1 0 0 1 0 1 0 0 1
1 1 1 0 0 1 1 1 0
1 0 0 0 1
S =AB 1 0 1 1 0
Cout = AB 1 1 0 1 0
1 1 1 1 1

S = A B Cin
Cout = AB + ACin + BCin

Chapter 5 <5>
 Multibit Adders (CPAs)
Types of carry propagate adders (CPAs):
Ripple-carry (slow)
Carry-lookahead (fast)
Prefix (faster)
Carry-lookahead and prefix adders faster for large adders
but require more hardware
Symbol
A B
N N

Cout Cin
+
N
S
Chapter 5 <6>
 Ripple-Carry Adder
Chain 1-bit adders together
Carry ripples through entire chain
Disadvantage: slow

A31 B31 A30 B30 A1 B1 A0 B0

Cout Cin
+ C30 + C29 C1 + C0 +
S31 S30 S1 S0

Chapter 5 <7>
Ripple-Carry Adder Delay

tripple = NtFA
where tFA is the delay of a full adder

Chapter 5 <8>
 Carry-Lookahead Adder
Compute carry out (Cout) for k-bit blocks using generate and
propagate signals
Some definitions:
Column i produces a carry out by either generating a carry out or
propagating a carry in to the carry out
Generate (Gi) and propagate (Pi) signals for each column:
Column i will generate a carry out if Ai AND Bi are both 1.

G i = Ai B i
Column i will propagate a carry in to the carry out if Ai OR Bi is 1.

Pi = Ai + Bi
The carry out of column i (Ci) is:

Ci = Ai Bi + (Ai + Bi )Ci-1 = Gi + Pi Ci-1

Chapter 5 <9>
 Carry-Lookahead Addition
Step 1: Compute Gi and Pi for all columns
Step 2: Compute G and P for k-bit blocks
Step 3: Cin propagates through each k-bit
propagate/generate block

Chapter 5 <10>
 Carry-Lookahead Adder
Example: 4-bit blocks (G3:0 and P3:0) :
G3:0 = G3 + P3 (G2 + P2 (G1 + P1G0 )
P3:0 = P3P2 P1P0

Generally,
Gi:j = Gi + Pi (Gi-1 + Pi-1 (Gi-2 + Pi-2Gj )
Pi:j = PiPi-1 Pi-2Pj
Ci = Gi:j + Pi:j Ci-1

Chapter 5 <11>
32-bit CLA with 4-bit Blocks
B31:28 A31:28 B27:24 A27:24 B7:4 A7:4 B3:0 A3:0

4-bit CLA C27 4-bit CLA C23 C7 4-bit CLA C3 4-bit CLA
Cout Cin
Block Block Block Block

S31:28 S27:24 S7:4 S3:0

B3 A3 B2 A2 B1 A1 B0 A0
C2 C1 C0
Cin
+ + + +
S3 S2 S1 S0

G3:0 G3
P3
G2
P2
G1
P1
G0

P3
Cout P3:0 P2
P1
Cin
P0

Chapter 5 <12>
 Carry-Lookahead Adder Delay
For N-bit CLA with k-bit blocks:
tCLA = tpg + tpg_block + (N/k 1)tAND_OR + ktFA

tpg : delay to generate all Pi, Gi

tpg_block : delay to generate all Pi:j, Gi:j
tAND_OR : delay from Cin to Cout of final AND/OR gate in k-bit CLA
block

An N-bit carry-lookahead adder is generally much faster than a

ripple-carry adder for N > 16

Chapter 5 <13>
 Prefix Adder
Computes carry in (Ci-1) for each column, then
computes sum:
Si = (Ai Bi) Ci
Computes G and P for 1-, 2-, 4-, 8-bit blocks, etc.
until all Gi (carry in) known
log2N stages

Chapter 5 <14>
 Prefix Adder
Carry in either generated in a column or propagated from a
previous column.
Column -1 holds Cin, so
G-1 = Cin, P-1 = 0
Carry in to column i = carry out of column i-1:
Ci-1 = Gi-1:-1
Gi-1:-1: generate signal spanning columns i-1 to -1
Sum equation:
Si = (Ai Bi) Gi-1:-1
Goal: Quickly compute G0:-1, G1:-1, G2:-1, G3:-1, G4:-1, G5:-1,
(called prefixes)

Chapter 5 <15>
Chapter 5 <16>
 Prefix Adder
Generate and propagate signals for a block spanning bits i:j:
Gi:j = Gi:k + Pi:k Gk-1:j
Pi:j = Pi:kPk-1:j
In words:
Generate: block i:j will generate a carry if:
upper part (i:k) generates a carry or
upper part propagates a carry generated in lower part
(k-1:j)
Propagate: block i:j will propagate a carry if both the
upper and lower parts propagate the carry

Chapter 5 <17>
Prefix Adder Schematic
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -1

14:13 12:11 10:9 8:7 6:5 4:3 2:1 0:-1

14:11 13:11 10:7 9:7 6:3 5:3 2:-1 1:-1

14:7 13:7 12:7 11:7 6:-1 5:-1 4:-1 3:-1

14:-1 13:-1 12:-1 11:-1 10:-1 9:-1 8:-1 7:-1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Legend i i
i:j

Ai Bi Pi:k Pk-1:jGi:k Gk-1:j Gi-1:-1 Ai Bi

Pi:i Gi:i

Pi:j Gi:j
Si
Chapter 5 <18>
Prefix Adder Delay
tPA = tpg + log2N(tpg_prefix ) + tXOR

tpg: delay to produce Pi Gi (AND or OR gate)

tpg_prefix: delay of black prefix cell (AND-OR gate)

Chapter 5 <19>
 Adder Delay Comparisons
Compare delay of: 32-bit ripple-carry, carry-lookahead, and
prefix adders
CLA has 4-bit blocks
2-input gate delay = 100 ps; full adder delay = 300 ps

Chapter 5 <20>
 Adder Delay Comparisons
Compare delay of: 32-bit ripple-carry, carry-lookahead, and
prefix adders
CLA has 4-bit blocks
2-input gate delay = 100 ps; full adder delay = 300 ps
tripple = NtFA = 32(300 ps)
= 9.6 ns
tCLA = tpg + tpg_block + (N/k 1)tAND_OR + ktFA
= [100 + 600 + (7)200 + 4(300)] ps
= 3.3 ns
tPA = tpg + log2N(tpg_prefix ) + tXOR
= [100 + log232(200) + 100] ps
= 1.2 ns
Chapter 5 <21>
Subtracter

Symbol Implementation
A B
N
A B
N N
N N
-
N +
Y N
Y

Chapter 5 <22>
Comparator: Equality

Symbol Implementation
A3
B3

A B A2
4 4 B2
Equal
= A1
B1
Equal
A0
B0

Chapter 5 <23>
 Comparator: Less Than

A B
N N

-
N
[N-1]

A<B

5-<24>
Copyright 2007 Elsevier
Chapter 5 <24>
 Arithmetic Logic Unit (ALU)

F2:0 Function
A B 000 A&B
N N 001 A|B
010 A+B
ALU 3F 011 not used
N 100 A & ~B
Y 101 A | ~B
110 A-B
111 SLT

5-<25>
Copyright 2007 Elsevier
Chapter 5 <25>
 ALU Design
A B
N N F2:0 Function
000 A&B
N
001 A|B
1

0 F2
N 010 A+B
011 not used
Cout + 100 A & ~B
[N-1] S
101 A | ~B
Extend
Zero

110 A-B
N N N N
1

0
3

2 F1:0 111 SLT

N
Y
5-<26>
Copyright 2007 Elsevier
Chapter 5 <26>
 Set Less Than (SLT) Example
A B
N N
Configure 32-bit ALU for SLT
operation: A = 25 and B = 32
N
1

0
F2
N

Cout +
[N-1] S
Extend
Zero

N N N N
1

0
3

2 F1:0
N
Y

5-<27>
Copyright 2007 Elsevier
Chapter 5 <27>
 Set Less Than (SLT) Example
A B
N N
Configure 32-bit ALU for SLT
operation: A = 25 and B = 32
N
1 A < B, so Y should be 32-bit
0
F2 representation of 1 (0x00000001)
N
F2:0 = 111
F2 = 1 (adder acts as
Cout + subtracter), so 25 - 32 = -7
[N-1] S
-7 has 1 in the most
Extend

significant bit (S31 = 1)

Zero

N N N N
F1:0 = 11 multiplexer selects
1

0
3

2 F1:0 Y = S31 (zero extended) =

N
Y
0x00000001.

5-<28>
Copyright 2007 Elsevier
Chapter 5 <28>
 Shifters
Logical shifter: shifts value to left or right and fills empty spaces with 0s
Ex: 11001 >> 2 =
Ex: 11001 << 2 =

Arithmetic shifter: same as logical shifter, but on right shift, fills empty
spaces with the old most significant bit (msb).
Ex: 11001 >>> 2 =
Ex: 11001 <<< 2 =

Rotator: rotates bits in a circle, such that bits shifted off one end are
shifted into the other end
Ex: 11001 ROR 2 =
Ex: 11001 ROL 2 =

5-<29>
Copyright 2007 Elsevier
Chapter 5 <29>
 Shifters
Logical shifter:
Ex: 11001 >> 2 = 00110
Ex: 11001 << 2 = 00100
Arithmetic shifter:
Ex: 11001 >>> 2 = 11110
Ex: 11001 <<< 2 = 00100
Rotator:
Ex: 11001 ROR 2 = 01110
Ex: 11001 ROL 2 = 00111

Chapter 5 <30>
Shifter Design
A 3 A 2 A1 A0 shamt1:0
2
00 S1:0
01

10
Y3

shamt1:0 11

2 00
S1:0
01
Y2
A3:0 4 >> 4 Y3:0
10

11

00
S1:0
01

10
Y1
11

00
S1:0
01

10
Y0
11

Chapter 5 <31>
Chapter 5 <32>
 Shifters as Multipliers, Dividers

A << N = A 2N
Example: 00001 << 2 = 00100 (1 22 = 4)
Example: 11101 << 2 = 10100 (-3 22 = -12)
A >>> N = A 2N
Example: 01000 >>> 2 = 00010 (8 22 = 2)
Example: 10000 >>> 2 = 11100 (-16 22 = -4)

Chapter 5 <33>
 Multipliers
Partial products formed by multiplying a single
digit of the multiplier with multiplicand
Shifted partial products summed to form result
Decimal Binary
230 multiplicand 0101
x 42 multiplier x 0111
460 partial 0101
+ 920 products 0101
9660 0101
+ 0000
result 0100011

230 x 42 = 9660 5 x 7 = 35

Chapter 5 <34>
 4 x 4 Multiplier
A B
4 4

x
8

P
A3 A2 A1 A0

B0
B1
0

A3 A2 A1 A0 0
x B3 B2 B1 B0 B2
A3B0 A2B0 A1B0 A0B0
A3B1 A2B1 A1B1 A0B1 0
B3
A3B2 A2B2 A1B2 A0B2
+ A3B3 A2B3 A1B3 A0B3
0
P7 P6 P5 P4 P3 P2 P1 P0
P7 P6 P5 P4 P3 P2 P1 P0

Chapter 5 <35>
FIRST VERSION OF MULTIPLICATION HARDWARE

Chapter 5 <36>
Chapter 5 <37>
4 x 4 Divider
0 B3 0 B2 0 B1 A3 B0
Legend
R B
1 R B
Cout Cin Cout Cin
Q3
+
D
D
N R'
A2

0
N
1
R'
Q2 A/B = Q + R/B
A1 Algorithm:
R = 0
1
for i = N-1 to 0
Q1
R = {R << 1. Ai}
A0
D=R-B
1 if D < 0, Qi=0, R=R
Q0 else Qi=1, R=D
R3 R2 R1 R0
R=R
Chapter 5 <38>
 Number Systems
Numbers we can represent using binary
representations
Positive numbers
Unsigned binary
Negative numbers
Twos complement
Sign/magnitude numbers

What about fractions?

Chapter 5 <39>
 Numbers with Fractions
Two common notations:
Fixed-point: binary point fixed
Floating-point: binary point floats to the right of the
most significant 1

Chapter 5 <40>
 Fixed-Point Numbers
6.75 using 4 integer bits and 4 fraction bits:

01101100
0110.1100
2 1 -1 -2
2 + 2 + 2 + 2 = 6.75
Binary point is implied
The number of integer and fraction bits must be
agreed upon beforehand

Chapter 5 <41>
 Fixed-Point Number Example
Represent 7.510 using 4 integer bits and 4
fraction bits.

Chapter 5 <42>
 Fixed-Point Number Example
Represent 7.510 using 4 integer bits and 4
fraction bits.

01111000

Chapter 5 <43>
 Signed Fixed-Point Numbers
Representations:
Sign/magnitude
Twos complement
Example: Represent -7.510 using 4 integer and 4 fraction
bits
Sign/magnitude:

Twos complement:

Chapter 5 <44>
 Signed Fixed-Point Numbers
Representations:
Sign/magnitude
Twos complement
Example: Represent -7.510 using 4 integer and 4 fraction
bits
Sign/magnitude:
11111000
Twos complement:
1. +7.5: 01111000
2. Invert bits: 10000111
3. Add 1 to lsb: + 1
10001000

Chapter 5 <45>
 Floating-Point Numbers
Binary point floats to the right of the most significant 1
Similar to decimal scientific notation

For example, write 27310 in scientific notation:

273 = 2.73 102
In general, a number is written in scientific notation as:
M BE
M = mantissa
B = base
E = exponent
In the example, M = 2.73, B = 10, and E = 2

Chapter 5 <46>
 Floating-Point Numbers

1 bit 8 bits 23 bits

Sign Exponent Mantissa

Example: represent the value 22810 using a 32-bit floating

point representation

We show three versions final version is called the IEEE 754

floating-point standard

Chapter 5 <47>
 Floating-Point Representation 1
1. Convert decimal to binary (dont reverse steps 1 & 2!):
22810 = 111001002
2. Write the number in binary scientific notation:
111001002 = 1.110012 27
3. Fill in each field of the 32-bit floating point number:
The sign bit is positive (0)
The 8 exponent bits represent the value 7
The remaining 23 bits are the mantissa
1 bit 8 bits 23 bits
0 00000111 11 1001 0000 0000 0000 0000
Sign Exponent Mantissa

Chapter 5 <48>
 Floating-Point Representation 2
First bit of the mantissa is always 1:
22810 = 111001002 = 1.11001 27
So, no need to store it: implicit leading 1
Store just fraction bits in 23-bit field

1 bit 8 bits 23 bits

0 00000111 110 0100 0000 0000 0000 0000
Sign Exponent Fraction

Chapter 5 <49>
 Floating-Point Representation 3
Biased exponent: bias = 127 (011111112)
Biased exponent = bias + exponent
Exponent of 7 is stored as:
127 + 7 = 134 = 0x100001102
The IEEE 754 32-bit floating-point representation of 22810

1 bit 8 bits 23 bits

0 10000110 110 0100 0000 0000 0000 0000
Sign Biased Fraction
Exponent

in hexadecimal: 0x43640000
Chapter 5 <50>
 Floating-Point Example
Write -58.2510 in floating point (IEEE 754)

Chapter 5 <51>
 Floating-Point Example
Write -58.2510 in floating point (IEEE 754)
1. Convert decimal to binary:
58.2510 = 111010.012
2. Write in binary scientific notation:
1.1101001 25
3. Fill in fields:
Sign bit: 1 (negative)
8 exponent bits: (127 + 5) = 132 = 100001002
23 fraction bits: 110 1001 0000 0000 0000 0000
1 bit 8 bits 23 bits
1 100 0010 0 110 1001 0000 0000 0000 0000
Sign Exponent Fraction
in hexadecimal: 0xC2690000

Chapter 5 <52>
 Floating-Point Precision
Single-Precision:
32-bit
1 sign bit, 8 exponent bits, 23 fraction bits
bias = 127

Double-Precision:
64-bit
1 sign bit, 11 exponent bits, 52 fraction bits
bias = 1023

Chapter 5 <54>
 Floating-Point Addition
1. Extract exponent and fraction bits
2. Prepend leading 1 to form mantissa
3. Compare exponents
4. Shift smaller mantissa if necessary
5. Add mantissas
6. Normalize mantissa and adjust exponent if necessary
7. Round result
8. Assemble exponent and fraction back into floating-point
format

Chapter 5 <56>
 Floating-Point Addition Example
Add the following floating-point numbers:
7.875 and 0.1875

Chapter 5 <57>
Chapter 5 <58>