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Timing Issues
CLK
In Combinational
R1 R2
Cin Logic Cout Out
D Q
Clk
T
Clk PWm
tsu
D
thold
tc-q td-q
Q
D Q
Clk
T
Clk
D thold
tsu
tc-q
Q
Clk tJS
delay delay
(a) Positive skew
R1 R2 R3
In Combinational Combinational
D Q D Q D Q
Logic Logic
TCLK + d
TCLK
1 3
CLK1
d
CLK2 2 4
d + th
TCLK + d
TCLK
1 3
CLK1
CLK2 2 4
d
tc - q tlogic
tc - q, cd tlogic, cd
tsu, thold
tc - q tlogic
tc - q, cd tlogic, cd
tsu, thold
REGS Combinational
In Logic
CLK t log ic
tc-q , tc-q, cd t log ic, cd
ts u, thold
tjitter
TJI +
TSU
Clk
TClk-Q
TLM
T
Minimum cycle time is determined by the maximum delays through the logic
Clk
TClk-Q TLm
Clk
TH
REG
REG
REG
. log Out
REG
In
Positive Skew
Clock Distribution
TSU
Flip TClk-Q
-flop
=1
=0
Logic
Representation after
M. Horowitz, VLSI Circuits 1996.
TSU
TSU TClk-Q
TClk-Q
=1
=1 =0
=0
Logic delay
Precharge Evaluate Precharge
Evaluate
Clk
Latch
Logic
Clk
PW
P
L1 L2
Logic
Latch Latch
Logic
CLK1
CLK2
a valid e valid
b valid c valid d valid
L2 latch
L1
Logic
L2 =1
Latch Latch
L1 latch
Logic
Long =0
path
H-tree
CLK
[Restle98]
Driver
Driver
Driver
GCLK GCLK
No rc-matching
Large power
Driver
GCL K
+ widely dispersed
NCLK
(Mem Ctrl) drivers
+ DLLs compensate
DLL
DLL
DLL
static and low-
frequency variation
+ divides design and
verification effort
(L2 Cache)
(L2 Cache)
L2R_CLK
L2L_CLK
PLL
38
Digital Integrated Circuits2nd Timing Issues
Self-timed and Asynchronous Design
Functions of clock in synchronous design
1) Acts as completion signal
2) Ensures the correct ordering of events
Self-timed design
R1 R2 R3 R4
In Logic Logic Logic
D Q Block #1 D Q Block #2 D Q Block #3 D Q
R1 F1 R2 F2 R3 F3 Out
In
LOGIC
In Out
NETWORK
Start B0
Done
B1
B0 B1
In1
In1
In2 PDN PDN
In2
Start
Start C2 C2
C1 C1
VDD
Start
Start
P0 P1 P2 P3
C0 C1 C2 C3 C4 C4 (b) Completion signal
C0 K0 K1 K2 K3
Start
VDD
Input Register
Start
Inputs Static CMOS Logic Output tdelay
A
GNDsense toverlap
Start
Current Sensor A B
tMDG
Done tpd-NOR
Done
Min Delay Generator B
Output valid
A B
A
S Q
F B
B F
R A F
B
(a) Logic
A B
B
(c) Dynamic
Digital Integrated Circuits2nd Timing Issues
48
2-Phase Handshake Protocol
In Out
R1 R2 R3
En Done
Reqi Req0
C C C
Acki Acko
From [Horowitz]
VDD
Post-charge
int
out logic
A B C
VDD
Q1 (also D2)
D1 Pulldown
Network
fin
Synchronous system
Asynchronous
system
fCLK
Synchronization
I1
int
D Q
I2
CLK
Vout
1.0
0.0
0 100 200 300
time [ps]
logarithmic
reduction
T
0 VIL VIH
Still Uniform
Initial Distribution
Q 2
In O1 O2 Out
Sync Sync Sync
Data
Digital Digital
System System
reference
fsystem = N x fcrystal clock
Divider PLL
PLL Clock
Buffer
fcrystal , 200<Mhz
Crystal
Oscillator
Reference Up
clock vcont
Phase Charge Loop
VCO
detector pump filter
Local Down
clock
Divide by
N
System
Clock
Transfer
characteristic
A UP = 0 UP = 0 UP = 1
A
DN = 1 DN = 0 DN = 0
Rst
D Q
DN
A B
B
(a) schematic (b) state transition diagram
A A
B B
UP UP
DN DN
UP
DN
Average (UP-DN)
VDD
-2 p
DN
fREF U
Phase Charge
D DL
Det Pump
Filter
fO
PD D CP VCO
N Filter
fO
CP/LF
Phase
Detector
Digital
GLOBAL CLK VCDL
Circuit
CP/LF
Phase
Detector