Basic Input and Output

One of the basic features of a computer is its

ability to exchange data with other devices.
Computers should have the ability to
exchange digital and analog information with
a wide range of devices in many different
environments.
Accessing I/O devices
The components of a computer system
communicate with each other through an
interconnection network.
 The interconnection network consists of
circuits needed to transfer information
between the processor, the memory unit, and
a number of I/O devices.
Typically Load and Store instructions use
addressing modes to generate effective
addresses that identify the desired locations.
The same instructions are extended to access
I/O devices as well.
Each I/O device appears to the processor as
consisting of some addressable locations, just
like the memory.
 The interconnection network is a bus that
enables all the devices to exchange information.
It consists of 3 lines used to carry address, data
and control signals.
Every I/O device has a unique address.
The processor places the particular address on
the address lines and the device that recognizes
this address responds to the commands.
The device sends the data across the data lines.
When the I/O device and the memory share same
address space the arrangement is called memory
mapped I/O.
 The I/O devices are associated with the
buffers.
DATAIN- input buffer
DATAOUT- Output buffer.
The instructions to access the I/O devices:
Move DATAIN, R0
Move R0, DATAOUT.
 In some processors I/O are performed using
separate instructions.
For example- intel processors use separate
instructions and 16-bit address space for I/O
devices.
In these systems, there are two options to
connect the I/O devices.
1. incorporate special address space.
2. Incorporate as a part of memory address space.
 Advantage of separate address space is that I/O
devices deal with fewer lines.
Separate address space for I/O - a special control
signal is asserted for reading/writing to the device.
The memory unit ignores such signals.
I/O Interface for an input device(Hardware )
Address lines
Bus Data lines
Control lines

Address Control Data and I/O

decoder circuits status registers interface

Input device
 I/O device is connected to the bus using an I/O
interface circuit which has:
- Address decoder, control circuit, and data and
status registers.
Address decoder decodes the address placed on
the address lines thus enabling the device to
recognize its address.
Data register holds the data being transferred to or
from the processor.
Status register holds information necessary for the
operation of the I/O device.
Data and status registers are connected to the data
lines, and have unique addresses.
I/O interface circuit coordinates I/O transfers.
 The rate of transfer to and from I/O devices is
slower than the speed of the processor.
This creates the need for mechanisms to
synchronize data transfers between them.
Program-controlled I/O:
Processor repeatedly monitors a status flag to achieve the necessary
synchronization- Processor polls the I/O device.

Two other mechanisms used for synchronizing

data transfers between the processor and
memory:
Interrupts.
Direct Memory Access.
Registers in keyboard and display interface

DATAIN

DATAOUT

STATUS DIRQ KIRQ SOUT SIN

CONTROL DEN

7 6 5 4 3 2 1 0
 The program reads a line of characters from the
keyboard and stores it in a memory buffer starting
at a location LINE.
A subroutine SUB is called to process input line.
As the character is read, it is echoed back to the
display.
Register R0 is used as a pointer to the buffer area,
contents are updated using autoincrement mode.
Each character is checked to see if Carriage
Return character(0D) and Line feed character
(0A) is entered to move the cursor down.
Example for programmed control I/O
Move #Line, R0 // Initialize memory pointer.
Waitk TestBit #0, STATUS //Test SIN
Branch =0 Waitk // Wait for character to be entered
Move DATAIN, R1 // read the character
Waitd TestBit #1, STATUS // Test SOUT
Branch =0 Waitd // Wait for display
Move R1, DTATAOUT // Send character for display
Move R1, (R0)+ // Store character and advance
Compare #$0D, R1 // Check for \r
Branch 0 Waitk // if not read another character
Move #$0A, DATAOUT // send \n to DATAOUT
Call SUB
Interrupts
In program-controlled I/O, when the processor
continuously monitors the status of the device, it does
not perform any useful tasks.
An alternate approach would be for the I/O device to
alert the processor when it becomes ready.
Do so by sending a hardware signal called an interrupt to the processor.
At least one of the bus control lines, called an interrupt-request line is
dedicated for this purpose.
Processor can perform other useful tasks while it is
waiting for the device to be ready.
One line of bus control lines carries interrupt called as
interrupt request line
 Program Interrupt Service Routine
1

Interrupt
occurs i
here
i +1

Processor is executing the instruction located at address i when an interrupt

occurs.
Routine executed in response to an interrupt request is called the interrupt-
service routine.
When an interrupt occurs, control must be transferred to the interrupt
service routine.
But before transferring control, the current contents of the PC (i+1), must
be saved in a known location.
This will enable the return-from-interrupt instruction to resume execution
at i+1.
Return address, or the contents of the PC are usually stored on the
processor stack.
 Treatment of an interrupt-service routine is very
similar to that of a subroutine.
However there are significant differences:
A subroutine performs a task that is required by the calling program.
Interrupt-service routine may not have anything in common with the
program it interrupts.
Interrupt-service routine and the program that it interrupts may belong to
different users.
As a result, before branching to the interrupt-service routine, not only
the PC, but other information such as condition code flags, and
processor registers used by both the interrupted program and the
interrupt service routine must be stored.
This will enable the interrupted program to resume execution upon
return from interrupt service routine.
 Saving and restoring information can be done automatically by
the processor or explicitly by program instructions.
Saving and restoring registers involves memory transfers:
Increases the total execution time.
Increases the delay between the time an interrupt request is received,
and the start of execution of the interrupt-service routine. This delay is
called interrupt latency.
In order to reduce the interrupt latency, most processors save
only the minimal amount of information:
This minimal amount of information includes Program Counter and
processor status registers.
Any additional information that must be saved, must be saved
explicitly by the program instructions at the beginning of the
interrupt service routine.
 When a processor receives an interrupt-
request, it must branch to the interrupt service
routine.
It must also inform the device that it has
recognized the interrupt request.
This can be accomplished in two ways:
Some processors have an explicit interrupt-acknowledge
control signal for this purpose.
In other cases, the data transfer that takes place between the
device and the processor can be used to inform the device.
Interrupt Hardware
An I/O device requests an interrupt by activating a bus line
called interrupt-request line.
A single interrupt-request line is used to serve n devices.

Devices are connected to the line via switches to the ground.

 If all interrupt requests are inactive then the
voltage on the line is Vdd.
A device raises the interrupt by closing the switch.
By this the voltage on the line drops to 0 causing
INTR signal to the processor to 1.
Closing of more than one switches also causes the
line voltage to drop to 0
The value of INTR is logical OR of the requests
from individual device.
INTR= INTR1+INTR2....+INTRn
INTR line is usually implemented in
complemented form, it is active in low-voltage
state.
Enabling and Disabling Interrupts.
Interrupt-requests interrupt the execution of a
program, and may alter the intended sequence of
events:
Sometimes such alterations may be undesirable, and must not be
allowed.
Any device that activates the interrupt-request
signal, it keeps it activated until it learns that
processor has accepted its request.
It is essential to ensure that this active signal does
not lead to successive interruptions.
For example, the processor may not want to be
interrupted by the same device while executing its
interrupt-service routine.
Processors generally provide the ability to enable
and disable such interruptions as desired.
(Assumption: Single interrupt request from one
device.)
First solution is to provide machine instructions
such as Interrupt-enable and Interrupt-disable for
this purpose.
To avoid interruption by the same device during
the execution of an interrupt service routine:
First instruction of an interrupt service routine can be
Interrupt-disable.
Last instruction of an interrupt service routine can be
Interrupt-enable.
 Second solution is to have the processor
automatically disable the interrupts before starting
execution of ISR- suitable for only one interrupt
request line.
The processor status register (PS) has the interrupt
enable bit that stores the information whether the
interrupt is raised.
An interrupt is received when this bit is 1.
To service this interrupt the processor stores PS
with bit set to 1 and contents of PC on the stack.
It then clears this bit to disable further interrupts.
The return from interrupt instruction restores the
contents of PS, setting interrupt-enable bit to 1.
 Third Option: the processor has a special
interrupt request line for which the interrupt
handling circuit responds to leading edge of
the signal.
The processor gets an interrupt when the line
changes from inactive to active state, but only
once.
To get a new request, the line must go back to
inactive and then to active again.
The sequence of evens involved in handling the
interrupt request from a single device:
1. The device raises an interrupt request.
2. The processor interrupts the program currently
being executed.
3. Interrupts are disabled by changing the bits in
PS.
4. The device is informed that its request has been
recognized and in response it deactivates the
interrupt request signal.
5. The action requested by the interrupt is
performed by ISR.
6. Interrupts are enabled and execution of the
interrupted program is resumed.
Handling Multiple devices.
Multiple I/O devices may be connected to the processor and
the memory via a bus.
Some or all of these devices may be capable of generating
interrupt requests.
Each device operates independently, and hence no definite
order can be imposed on how the devices generate interrupt
requests.
The obvious questions are:
How does the processor know which device has generated
an interrupt?
How does the processor know which interrupt service
routine needs to be executed?
When the processor is executing an interrupt service routine
for one device, can other device interrupt the processor?
If two interrupt-requests are received simultaneously, then
how to break the tie?
1. How does the processor know which device has generated
an interrupt?
Devices send their interrupt-requests over a single control
line in the bus.
The processor receives an interrupt request over this control
line.
The information of which device has raised the interrupt is
there in the status register of each device.
The status register has an IRQ bit is sets to 1 when it
requests an interrupt.
To identify the interrupting device there can be Interrupt
service routine that can poll the I/O devices connected to
the bus.
The first device with IRQ equal to 1 is the one that is
serviced.
Polling mechanism is easy, but time consuming to query the
status bits of all the I/O devices connected to the bus.
Vectored Interrupts.
To reduce the time involved in the polling
process, a device requesting an interrupt may
identify itself directly to the processor.
The processor can immediately start executing
the corresponding interrupt-service routine.
This type of interrupt handling is called
vectored interrupts.
2. How does the processor know which interrupt service
routine needs to be executed?
The device requesting an interrupt may identify itself
directly to the processor.
Device can do so by sending a special code (4 to 8 bits) the
processor over the bus.
Code supplied by the device may:
1. Represent a part of the starting address of the interrupt-service
routine.
The remainder of the starting address is obtained by the
processor based on other information such as the range of
memory addresses where interrupt service routines are located.
2. It may used as pointer to point the starting address of the
interrupt-service routine.
These addresses are usually referred to as interrupt vectors, and
they are said to point to the interrupt-vector table.
 The interrupt-service routines may be located
anywhere in the memory.
When an interrupt request arrives, the
information provided by the requesting device
is used as a pointer into the interrupt-vector
table.
The address in the corresponding interrupt
vector table is automatically loaded into the
program counter.
3. When the processor is executing an interrupt service
routine for one device, can other device interrupt the
processor?
Interrupts are disabled during the execution of an
interrupt-service routine, to ensure that a request from
one device will not cause more than one interruption.
Execution of a given interrupt-service routine, once
started, always continues to completion before the
processor accepts an interrupt request from a second
device.
Interrupt-service routines are typically short, and the
delay they may cause is acceptable for most simple
devices.
For certain devices this delay may not be acceptable.
For example, a computer that keeps track of the time of day
using a real-time clock.
This is a device that sends interrupt requests to the
processor at regular intervals.
 To ensure that this requirement is satisfied, it
may be necessary to accept an interrupt request
during the execution of an interrupt-service
routine for another device, i.e., to nest
interrupts.
Hence I/O devices should be organized in a
priority structure.
An interrupt request from a high-priority
device should be accepted while the processor
is servicing a request from a lower-priority
device.
Multiple-level Priority Organization
During execution of an interrupt service routine, interrupt
requests will be accepted from some devices depending
upon the devices priority.
A priority level is assigned to a processor that can be
changed under program control.
The processors priority can be encoded in a few bits of the
processor status register.(using privileged instructions in
supervisor mode)
Implementation
Priority level of a processor is the priority of the program that is
currently being executed.
When the processor starts executing the interrupt service routine
of a device, its priority is raised to that of the device.
This action disables interrupts from devices that have the same
or lower level of priority.
If the device sending an interrupt request has a higher priority
than the processor, the processor accepts the interrupt request.
Implementation of multiple priority scheme
Each device has a separate interrupt-request and interrupt-acknowledge
line.
Each interrupt-request line is assigned a different priority level.
Interrupt requests received over these lines are sent to a priority arbitration
circuit in the processor.
If the interrupt request has a higher priority level than the priority of the
processor, then the request is accepted.

INTR1 I NTRp
Processor

Device 1 Device 2 Devicep

INTA1 INTA p

Priority arbitration
4. If two interrupt-requests are received
simultaneously, then how to break the tie?
The processor must have some means of deciding
which request to service first.
If the I/O devices are organized in a priority
structure, the processor accepts the interrupt
request from a device with higher priority.
Each device has its own interrupt request and interrupt
acknowledge line.
A different priority level is assigned to the interrupt
request line of each device.
If the devices share an interrupt request line, then
how does the processor decide which interrupt
request to accept?
Polling scheme:
If the processor uses a polling mechanism to
poll the status registers of I/O devices to
determine which device is requesting an
interrupt.
In this case the priority is determined by the
order in which the devices are polled.
The first device with status bit set to 1 is the
device whose interrupt request is accepted.
Commonly used schemes to connect devices.
1. Daisy chain scheme
I NTR
Processor

Device 1 Device 2 Device n

INTA

Devices are connected to form a daisy chain.

Devices share the interrupt-request line, and interrupt-acknowledge line
is connected to form a daisy chain.
When devices raise an interrupt request, the interrupt-request line is
activated.
The processor in response activates interrupt-acknowledge.
Received by device 1, if device 1 does not need service, it passes the
signal to device 2.
Device that is electrically closest to the processor has the highest
priority.
 Devices are organized into
2. An arrangement of Priority groups.
I NTR1 Each group is assigned a
different priority level.
Processor

Device Device
INTA1 All the devices within a single
group share an interrupt-
INTR p
request line, and are
connected to form a daisy
Device Device
INTA p chain.
Priority arbitration
circuit

When I/O devices were organized into a priority structure,

each device had its own interrupt-request and interrupt-
acknowledge line.
When I/O devices were organized in a daisy chain
fashion, the devices shared an interrupt-request line, and
the interrupt-acknowledge propagated through the
devices.
A combination of priority structure and daisy chain
scheme can also used.
Controlling Device Request
Only those devices that are being used in a program
should be allowed to generate interrupt requests.
To control which devices are allowed to generate
interrupt requests, the interface circuit of each I/O
device has an interrupt-enable bit.
If the interrupt-enable bit in the device interface is set
to 1, then the device is allowed to generate an interrupt-
request.
Interrupt-enable bit in the devices interface circuit
determines whether the device is allowed to generate an
interrupt request.
Interrupt-enable bit in the processor status register or
the priority structure of the interrupts determines
whether a given interrupt will be accepted.
Summary:
There are two independent mechanisms for
controlling interrupt requests.
1. At device end: an interrupt enable bit in the
control register determines whether the device
is allowed to generate an interrupt request.
2. At the processor end: either an interrupt
enable bit or priority structure determines
whether a given interrupt request will be
accepted.
Exceptions
An interrupt is an event that causes the execution
of one program to be suspended and the
execution of another program to begin.
Interrupts are not only caused by events
associated with I/O data transfers.
The interrupt mechanism is used in a number of
other situations.
The term exception is often used to refer to any
event that causes an interruption.
Hence, I/O interrupts are one example of an
exception.
Other types of exceptions are:
Recovery from errors
Debugging
Privilege exception
Recovery from errors
There are many sources of errors in a processor.
For example: Error in the data stored or Error during the execution
of an instruction.
When such errors are detected, exception processing is initiated.
Processor takes the same steps as in the case of I/O interrupt-
request.
It suspends the execution of the current program, and starts
executing an exception-service routine.
Difference between handling I/O interrupt-request and handling
exceptions due to errors:
In case of I/O interrupt-request, the processor usually completes the
execution of an instruction in progress before branching to the
interrupt-service routine.
In case of exception processing however, the execution of an
instruction in progress usually cannot be completed.
Debugging
The other scenario where exceptions are used is in the
case of debuggers.
Debuggers use exceptions to provide important
features such as tracing and breakpoints.
When the debugger is used in the trace mode, the
execution of the program needs to be stopped after
every instruction so that the contents of the variables
can be examined.
The way the trace mode is implemented is that
exception occurs after the execution of every
instruction, and the debugging program is used as the
exception service routine.
In case of breakpoints program execution is halted only
at specific points selected by the user.
Once again, the debugging program is used as the
exception service routine.
Privileged Exception
Certain instructions can be executed only
when the processor is in the supervisor mode.
These are called privileged instructions.
If an attempt is made to execute a privileged
instruction in the user mode, a privilege
exception occurs.
Privilege exception causes:
Processor to switch to the supervisor mode,
Execution of an appropriate exception-
servicing routine.
Direct Memory Access
Blocks of data are often transferred between the
main memory and I/O devices such as disks.
Generally single-word or single-byte data
transfers happens between the processor and I/O
devices.
Data are transferred from an I/O device to the
memory by first reading them from the I/O
device using an instruction such as
Move DATAIN, R0
Loads the data into a processor register.
Then, the data read are stored into a memory
location.
 An instruction to transfer input or output data is
executed only after the processor determines
that the I/O device is ready, either by polling its
status register or by waiting for an interrupt
request.
This leads to considerable overheads:
Program instructions must be executed involving
many memory accesses for each data word transfers.
With black transfer, instructions are needed to
increment the memory address and keep track of the
word count.
The use of interrupts involves operating system
routines which incur additional overhead to save and
restore processor registers, the program counter, and
other state information.
 This is resolved by a special control unit that manages
the transfer, without continuous intervention by the
processor.
This approach is called direct memory access, or DMA.
The unit that controls DMA transfers is referred to as a
DMA controller.
It may be part of the I/O device interface, or it may be
a separate unit shared by a number of I/O devices.
DMA controller performs functions that would be
normally carried out by the processor:
For each word, it provides the memory address and all the
control signals.
To transfer a block of data, it increments the memory
addresses and keeps track of the number of transfers.
 DMA controller can transfer a block of data from an
external device to the processor, without any
intervention from the processor.
However, the operation of the DMA controller must be
under the control of a program executed by the processor.
That is, the processor must initiate the DMA transfer.
To initiate the DMA transfer, the processor informs the
DMA controller of:
Starting address,
Number of words in the block.
Direction of transfer (I/O device to the memory, or
memory to the I/O device).
Once the DMA controller completes the DMA transfer,
it informs the processor by raising an interrupt signal.
Registers in DMA interface
 Two registers are used for storing the starting address
and the word count.
The third register contains status and control flags.
The R/W bit determines the direction of the transfer.
When this bit is set to 1 by a program instruction, the
controller performs a Read operation, that is, it
transfers data from the memory to the I/O device.
Otherwise, it performs aWrite operation.
Additional information is also transferred as may be
required by the I/O device.
For example, in the case of a disk, the processor
provides the disk controller with information to
identify where the data is located on the disk
 When the controller has completed
transferring a block of data and is ready to
receive another command, it sets the Done
flag to 1.
Bit 30 is the Interrupt-enable flag, IE.When
this flag is set to 1, it causes the controller to
raise an interrupt after it has completed
transferring a block of data.
Finally, the controller sets the IRQ bit to 1
when it has requested an interrupt.
Example:
EXAMPLE

Main
Processor
memory

System bus

Disk/DMA DMA Keyboard

controller controller Printer

Disk Disk Network

Interface

DMA controller connects a high-speed network to the computer bus.

Disk controller, which controls two disks also has DMA capability. It provides two
DMA channels.
It can perform two independent DMA operations, as if each disk has its own DMA
controller. The registers to store the memory address, word count and status and
control information are duplicated.
DMA performs data transfer operation.
The different DMA transfer modes are as follows:-
1) Burst or block transfer DMA
2) Cycle steal or single byte transfer DMA.
3) Transparent or hidden DMA.
1) Burst or block transfer DMA
It is the fastest DMA mode. In this two or more data bytes are transferred
continuously.
Processor is disconnected from system bus during DMA transfer.
N number of machine cycles are adopted from the machine cycles of the
processor where N is the number of bytes to be transferred.
DMA sends HOLD signal to processor to request for system bus and waits
for HLDA signal.
After receiving HLDA signal, DMA gains control of system bus and transfers
one byte.
After transferring one byte, it increments memory address, decrements counter
and transfers next byte.
In this way, it transfer all data bytes between memory and I/O devices.
After transferring all data bytes, the DMA controller disables HOLD signal
& enters into slave mode.
2) Cycle steal or single byte transfer DMA.
In this mode only one byte is transferred at a time.
This is slower than burst DMA.
DMA sends HOLD signal to processor and waits
for HLDA signal on receiving HLDA signal, it
gains control of system bus and executes only one
DMA cycle.
After transfer one byte, it disables HOLD signal
and enters into slave mode.
Processor gains control of system bus and
executes next machine cycle.
If count is not zero and data is available then the
DMA controller sends HOLD signal to the
processor and transfer next byte of data block.
3) Transparent or Hidden DMA transfer
Processor executes some states during which is
floats the address and data buses.
During this process, processor is isolated from
the system bus.
DMA transfers data between memory and I/O
devices during these states.
This operation is transparent to the processor.
This is slowest DMA transfer as the
transparent DMA requires logic to detect the
states when the processor is floating the buses.
Bus Arbitration
Processor and DMA controllers both need to initiate data
transfers on the bus and access main memory.
The device that is allowed to initiate transfers on the bus at
any given time is called the bus master.
When the current bus master relinquishes its status as the
bus master, another device can acquire this status.
The process by which the next device is selected to become
the bus master and bus mastership is transferred to it is
called bus arbitration.
Types:
Centralized arbitration:
A single bus arbiter performs the arbitration.
Distributed arbitration:
All devices participate in the selection of the
next bus master.
 Centralized Bus Arbitration

B BS Y

BR

Processor

DMA DMA
controller controller
BG1 1 BG2 2
 Bus arbiter may be the processor or a separate unit
connected to the bus.
The processor is the bus master, unless it grants bus
membership to one of the DMA controllers.
DMA controller requests the control of the bus by asserting
the Bus Request (BR) line.
In response, the processor activates the Bus-Grant1 (BG1)
line, indicating that the controller may use the bus when it
is free.
BG1 signal is connected to all DMA controllers in a daisy
chain fashion.
The current bus master indicates to all devices that it is
using the bus by activating Bus Busy signal.
BBSY signal is 0, it indicates that the bus is busy.
When BBSY becomes 1, the DMA controller which
asserted BR can acquire control of the bus.
Sequence of signals during transfer of bus master ship for the
device in centralized arbitration

DMA controller 2
asserts the BR signal. Time
Processor asserts
BR
the BG1 signal

BG1 BG1 signal propagates

to DMA#2.
BG2

BBSY

Bus
master
Processor DMA controller 2 Processor

Processor relinquishes control

of the bus by setting BBSY to 1.
Distributed Arbitration
All devices waiting to use the bus share the responsibility of carrying out
the arbitration process.
Arbitration process does not depend on a central arbiter and hence
distributed arbitration has higher reliability.
Each device is assigned a 4-bit ID number.
All the devices are connected using 5 lines, 4 arbitration lines to transmit
the ID, and one line for the Start-Arbitration signal.
To request the bus a device:
Asserts the Start-Arbitration signal.
Places its 4-bit ID number on the arbitration
lines.
The pattern that appears on the arbitration lines
is the logical-OR of all the 4-bit device IDs
placed on the arbitration lines.
Arbitration process:
Each device compares the pattern that appears
on the arbitration lines to its own ID, starting
with MSB.
If it detects a difference, it transmits 0s on the
arbitration lines for that and all lower bit
positions.
The pattern that appears on the arbitration lines
is the logical-OR of all the 4-bit device IDs
placed on the arbitration lines.
 Device A has the ID 5 and wants to request the
bus: - Transmits the pattern 0101 on the
arbitration lines.
Device B has the ID 6 and wants to request the
bus: - Transmits the pattern 0110 on the
arbitration lines.
Pattern that appears on the arbitration lines is
the logical OR of the patterns:
- Pattern 0111 appears on the arbitration
lines.
Arbitration process:
Each device compares the pattern that appears on the
arbitration lines to its own ID, starting with MSB.
If it detects a difference, it transmits 0s on the
arbitration lines for that and all lower bit positions.
Device A compares its ID 5 with a pattern 0101 to
pattern 0111.
It detects a difference at bit position 0, as a result, it
transmits a pattern 0100 on the arbitration lines.
The pattern that appears on the arbitration lines is the
logical-OR of 0100 and 0110, which is 0110.
This pattern is the same as the device ID of B, and
hence B has won the arbitration.
Busses
Processor, main memory, and I/O devices are
interconnected by means of a bus.
Bus provides a communication path for the
transfer of data.
Bus also includes lines to support interrupts
and arbitration.
A bus protocol is the set of rules that govern
the behavior of various devices connected to
the bus, as to when to place information on the
bus, when to assert control signals, etc.
 Bus lines may be grouped into three types:
Data
Address
Control
Control signals specify:
Whether it is a read or a write operation.
Required size of the data, when several operand sizes (byte,
word, long word) are possible.
Timing information to indicate when the processor and
I/O devices may place data or receive data from the
bus.
Schemes for timing of data transfers over a bus can be
classified into:
Synchronous,
Asynchronous.
 In any data transfer operation, one device plays
the role of a master.
This is the device that initiates data transfers
by issuing Read or Write commands on the
bus.
Normally, the processor acts as the master, but
other devices may also become masters.
The device addressed by the master is referred
to as a slave.
Synchronous Bus
In this bus all devices derive timing
information from a common clock line.
Equally spaced pulses on this line define equal
time intervals.
Each of these intervals constitutes a bus cycle
during which one data transfer can take place.
The address and data lines carry both highand
low signal levels at the same time.
Timing of an input transfer on a synchronous bus.
This is a common convention for indicating that some lines
are high and some low, depending on the particular address
or data values being
transmitted.
The crossing points indicate the times at which these
patterns change
 Timing diagram for input transfer

Time
Bus clock

Address and
command

Data

t0 t1 t2

Bus cycle
Master places the
device address and Addressed slave places
command on the bus, data on the data lines Master strobes the data
and indicates that on the data lines into its
it is a Read operation. input buffer, for a Read
operation.
In case of a Write operation, the master places the data on the bus along with the
address and commands at time t0.
The slave strobes the data into its input buffer at time t2.
 At the end of the clock cycle, at time t2, the
master strobes the data on the data lines into its
input buffer if its a Read operation.
Strobe means to capture the values of the data and
store them into a buffer.
When data are to be loaded into a storage buffer
register, the data should be available for a period
longer than the setup time of the device.
Width of the pulse t2 - t1 should be longer than:
Maximum propagation time of the bus plus
Set up time of the input buffer register of the master.
 Detailed timing diagram for input transfer
Time
Address & Bus clock
command Data reaches
Seen by
appear on the master t AM the master.
bus. Address and
command

Data
Address & t DM
command reach
Seen by slave
the slave. tAS
Address and Data appears
command on the bus.

Data
tDS

t0 t1 t
2
Signals do not appear on the bus as soon as they are placed on the bus, due to the
propagation delay in the interface circuits.
Signals reach the devices after a propagation delay which depends on the
characteristics of the bus.
Data must remain on the bus for some time after t2 equal to the hold time of the buffer.
Multiple cycle transfer
Disadvantage of previous approach:
1. Data transfer has to be completed within one clock
cycle.
2. Clock period t2 - t0 must be such that the longest
propagation delay on the bus and the slowest device
interface must be accommodated.
3. Forces all the devices to operate at the speed of the
slowest device.
4. The processor has no way of determining whether the
addressed device has actually responded.
At t2, it simply assumes that the input data are available
on the data lines in a Read operation, or that the output
data have been received by the I/O device in a Write
operation.
If, because of a malfunction, a device does not operate
correctly, the error will not be detected.
To overcome these limitations
Most buses have control signals to represent a
response from the slave.
Control signals serve two purposes:
Inform the master that the slave has recognized the
address, and is ready to participate in a data transfer
operation.
Enable to adjust the duration of the data transfer
operation based on the speed of the participating
slaves.
This is often accomplished by allowing a
complete data transfer operation to span several
clock cycles.
The number of clock cycles involved can vary
from one device to another.
 An input transfer using multiple clock cycles.
Address & command Time
requesting a Read
operation appear on 1 2 3 4
the bus.
Clock

Address

Command
Master strobes data
into the input buffer.
Data

Slave-ready

Slave places the data on the bus, Clock changes are seen by all the devices
and asserts Slave-ready signal. at the same time.
Asynchronous Bus
An alternative scheme for controlling data transfers on
a bus is based on the use of a handshake protocol
between the master and the slave.
Common clock in the synchronous bus case is replaced
by two timing control lines:
Master-ready,
Slave-ready.
Master-ready signal is asserted by the master to
indicate to the slave that it is ready to participate in a
data transfer.
Slave-ready signal is asserted by the slave in response
to the master-ready from the master, and it indicates
to the master that the slave is ready to participate in a
data transfer.
Handshake control of data transfer during an
input operation.
Data transfer using the handshake protocol:
Master places the address and command
information on the bus.
Asserts the Master-ready signal to indicate to the
slaves that the address and command
information has been placed on the bus.
All devices on the bus decode the address.
Address slave performs the required operation,
and informs the processor it has done so by
asserting the Slave-ready signal.
Master removes all the signals from the bus, once
Slave-ready is asserted.
If the operation is a Read operation, Master also
strobes the data into its input buffer.
 Handshake control of data transfer during an input operation.

Time
Address
and command

Master-ready

Slave-ready

Data

t0 t1 t2 t3 t4 t5

Bus cycle
t0 - Master places the address and command information on the bus.
t1 - Master asserts the Master-ready signal. Master-ready signal is asserted at t1 instead of t0
t2 - Addressed slave places the data on the bus and asserts the Slave-ready signal.
t3 - Slave-ready signal arrives at the master.
t4 - Master removes the address and command information.
t5 - Slave receives the transition of the Master-ready signal from 1 to 0. It removes the data
and the Slave-ready signal from the bus.
Asynchronous vs. Synchronous bus

Advantages of asynchronous bus:

Eliminates the need for synchronization between the sender and the receiver.

Can accommodate varying delays automatically, using the Slave-ready signal.

Disadvantages of asynchronous bus:

Data transfer rate with full handshake is limited by two-round trip delays.
Data transfers using a synchronous bus involves only one round trip delay, and
hence a synchronous bus can achieve faster rates.