MPI Unit 4

Unit-4
Assembly Language Basics

Prof. Swati Sharma
swati.sharma@darshan.ac.in
Microprocessor
Unit4
Unit4 Assembly
Assembly &
Microprocessor Language
& Interfacing
Language Basics
Interfacing
Basics2150707 1
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Subject Overview
Sr. No. Unit % Weightage
1 Introduction to Microprocessor 8%
2 Microprocessor Architecture and Operations 7%
3 8085 Microprocessor 10%
4 Assembly Language Basics 10%
5 8085 Assembly Language Programs 10%
6 Stack & Subroutines 10%
7 I/O Interfacing 15%
8 Advanced Microprocessors 20%
9 SUN SPARC Microprocessor 5%
10 ARM Processor 5%
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Assembly Language Programming Basics
3
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Hierarchy of Languages
Application Program
Machine Independent High Level Language High Level Language

Machine Specific Low Level Language
Assembly Language
Assembly language
is a low-level
MOV BL,05h
1100 1011 Machine Language programming
ADD CL 1100 1110 language
Native todesigned
a
MUL BH 0100 1111
forprocessor:
a specific type
Micro Program Control ofexecuted
processor.directly
by hardware
Uses symbolic
names
Instructions
to represent
Hardware consist of binary
operations,
code: 1sand
registers and 0s
memory locations.
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Compilers and Assemblers
High Level Language
Compiler
Compiler Assembly Language
Assembler
Machine Language
Compilers translate high-level programs translates

Assemblers to machine code code to machine code
assembly
either directly, or Indirectly via an assembler
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Instructions and Machine Language
Each command of a program is called an instruction (it instructs
the computer what to do).
Computers only deal with binary data, hence the instructions must
be in binary format (0s and 1s) .
The set of all instructions (in binary form) makes up the
computer's machine language. This is also referred to as the
instruction set.
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Instruction Fields
Assembly language instructions usually are made up of several
fields.
Each field specifies different information for the computer.
The major two fields are:
1. Opcode field which stands for operation code and it specifies the
particular operation that is to be performed.
Each operation has its unique opcode.
2. Operands fields which specify where to get the source and destination
operands for the operation specified by the opcode.
The source/destination of operands can be a constant, the memory or one
of the general-purpose registers.
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Instruction Fields
Opcode Operand
MOV Rd, Rs
M, Rs
Rs, M
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Translating Languages
English: D is assigned the sum of A and B
High-Level Language: D = A + B
A statement in a high-level language is translated

typically into several machine-level instructions
Assembly Language: Machine Language:

MVI A,02 1001 1011 1111
MVI B,03 1101 1011 1110
ADD B
1011 0011 1100
MOV D,A
1110 1010 1000
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Advantages of High-Level Languages
Program development is faster
High-level statements: fewer instructions to code
Program maintenance is easier
For the same above reasons
Programs are portable
Contain few machine-dependent details
Can be used with little or no modifications on different machines
Compiler translates to the target machine language
However, Assembly language programs are not portable
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Why to Learn Assembly Language?
Accessibility to system hardware
Assembly Language is useful for implementing system software
Also useful for small embedded system applications
Space and Time efficiency
Understanding sources of program inefficiency
Tuning program performance
Writing compact code
It is helpful for:
compiler writing
programming microcontrollers
device drivers
system design
low-level numeric routines
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Why to Learn Assembly Language?
Writing assembly programs gives the computer designer the
needed deep understanding of the instruction set and how to
design one
To be able to write compilers for HLLs, we need to be expert with
the machine language. Assembly programming provides this
experience
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Assembly Language Programming Tools
1. Assembler
2. Linker
3. Debugger
4. Editor
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Assembler
An assembler is a program that converts source-code programs
written in assembly language into object files in machine language
Popular assemblers have emerged over the years for the Intel
family of processors. These include
TASM (Turbo Assembler from Borland)
NASM (Netwide Assembler for both Windows and Linux), and
GNU assembler distributed by the free software foundation
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Linker
A linker program is required to produce executable files
It combines your program's object file created by the assembler
with other object files and link libraries, and produces a single
executable program
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Assemble and Link Process
Source Object
File Assembler File
Source Object Executable

File Assembler File Linker
File
Link
Source Object
Assembler Libraries
File File
A project may consist of multiple source files

Assembler translates each source file separately into an object file
Linker links all object files together with link libraries
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Debugger
Allows you to trace the execution of a program
Allows you to view code, memory, registers, etc.
Example: 32-bit Windows debugger
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Editor
Allows you to create assembly language source files
Some editors provide syntax highlighting features and can be
customized as a programming environment
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Classification
of
8085 Instructions
19
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Classification of 8085 Instructions
Based on Byte Size Based on Function

Data Transfer Instructions
One-byte Instructions
Arithmetic Instructions
Logic & Bit Manipulation

Two-byte Instructions Instructions
Branch Instructions
Control Instructions
Three-byte Instructions
20
An instruction is a binary pattern designed inside a microprocessor
to perform a specific function.
8085 has 246 instructions.
Each instruction is represented by an 8-bit binary value.
These 8-bits of binary value is called Op-Code.
The entire group of instructions that a microprocessor supports is
called Instruction Set.
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Instruction Set
It is the set of instructions that the microprocessor can understand.
Opcode
Known as 'Operation Code
This required field contains the mnemonic operation code for the 8085
instruction
Operand
The operand field identifies the data to be operated on by the specified
opcode.
Some instructions require no operands, while others require one or two
operands.
MVI D, 8BH
Opcode Operand
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General Terms
R 8085 8-bit register (A, B, C, D, E, H, L)
M Memory
Rs Register Source
Rd Register Destination
Rp Register Pair (BC, DE, HL)
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Branch Instructions
24
1-byte Instruction
1-byte instructions includes Opcode and Operand in the same byte.
Instruction Binary Code Hexa Code

Opcode Operand
MOV C,A 0100 1111 4FH
ADD B 1000 0000 80H
CMA 0010 1111 2FH
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Branch Instructions
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2-byte Instruction
In 2-byte instruction,
1st Byte : Specifies Operation code
2nd Byte: Specifies the Operand
Opcode Operand
MVI A,32H 0011 1110 3E: 1st Byte
0011 0010 32: 2nd Byte
MVI B,F2H 0000 0110 06: 1st Byte
1111 0010 F2: 2nd Byte
IN 0AH 1101 1011 DB: 1st Byte

0000 1010 0A: 2nd Byte
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Branch Instructions
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3-byte Instruction
In 3-byte instruction,
1st Byte: Specifies Opcode
2nd Byte: Specifies lower order 8-bit address
3rd Byte: Specifies higher order 8-bit address

Opcode Operand
LDA 2050H 0011 1010 3A: 1st Byte
0101 0000 50: 2nd Byte
0010 0000 20: 3rd Byte
JMP 2085H 1100 0011 C3: 1st Byte
1000 0101 85: 2nd Byte
0010 0000 20: 3rd Byte
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Requires one memory location
to perform an operation Arithmetic Instructions
E.g. CMA, ADD
Requires two memory locations
to perform an operation Branch Instructions
E.g. MVI A,32H
Requires three memory locations
to perform an operation
E.g. JMP, CALL
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These instructions copy data from source to destination.
While copying, the contents of source are not modified.
Data Transfer Instructions do not affects the flags.
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MOV: Move
Instruction Description Example

Opcode Operand
MOV R d, R s This instruction copies the contents MOV B, C

MOV M, R of the source register into the MOV E, D
MOV R, M destination register.
the contents of the source register
are not altered.
If one of the operands is a memory
location, its location is specified by
the contents of the HL registers.
This is 1-byte instruction
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MVI: Load 8-bit to Register/Memory

Opcode Operand
MVI M, Data The 8-bit data is stored in the MVI B, 57H

MVI R, Data destination register or memory. MVI D, 12H
If the operand is a memory location,
its location is specified by the
contents of the HL registers.
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LDA: Load Accumulator

Opcode Operand
LDA 16-bit The contents of a memory location, LDA 2050H

address specified by a 16-bit address in the LDA 0006H
operand, are copied to the
accumulator.
The contents of the source are not
altered.
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LDAX: Load the accumulator indirect

Opcode Operand
LDAX Rp The contents of a memory location, MVI B,00H

(B/D) specified by a 16-bit address in the MVI C,06H
operand, are copied to the LDAX B ; BC pair
accumulator.
The contents of the source are not MVI D,00H
altered. MVI E,0BH
LDAX D ; DE pair
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LDAX Instruction
Registers Memory
02 0001
A 0D
04 0002
B 00 06 C 0A 0003
06 0004
D E
0F 0005
H L 0D 0006
05 0007
03 0008
MVI B,00H
MVI C,06H
LDAX B ; BC pair
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LXI: Load the register pair immediate

Opcode Operand
LXI Rp, 16-bit The instruction loads 16-bit data in LXI H, 2034H
Data the register pair designated in the
operand.
A
B
D
H 20 34 L
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STA: Store Accumulator

Opcode Operand
STA 16-bit The contents of the accumulator are MVI A, 09H data
address copied into the memory location STA 0002H
specified by the operand.
16bit memory address
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STAX: Store Accumulator Indirect

Opcode Operand
STAX Rp The contents of the accumulator are STAX B

copied into the memory location
specified by the contents of the operand
(register pair). The contents of the
accumulator is not altered.
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LHLD: Load H and L registers direct

Opcode Operand
LHLD 16-bit The instruction copies the contents LHLD 2050H

address of the memory location pointed out LHLD 0006H
by the address into register L and
copies the contents of the next
memory location into register H.
The contents of source memory
locations are not altered.
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LHLD Instruction
Registers Memory
02 0001
A
04 0002
B C 0A 0003
06 0004
D E
0F 0005
H L 0D 0006
05 0007
03 0008
LHLD 0006H
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SHLD: Store H and L registers direct

Opcode Operand
SHLD 16-bit The contents of register L are stored in SHLD 0002H

address the memory location specified by the
16-bit address in the operand and the
contents of H register are stored into the
next memory location by incrementing
the operand.
Memory
0001
0002 SP
H A2 D3 L 0003 SP
0004
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XCHG: Exchange H and L with D and E

Opcode Operand
XCHG None The contents of register H are XCHG

exchanged with the contents of register
D, and the contents of register L are
exchanged with the contents of register
E.
D A2 03 E D D3 08 E
XCHG
H D3 08 L H A2 03 L
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SPHL: Copy H and L registers to the stack pointer

Opcode Operand
SPHL None The instruction loads the contents of the SPHL

H and L registers into the stack pointer
register, the contents of the H register
provide the high-order address and the
contents of the L register provide the
low-order address. The contents of the
H and L registers are not altered.
SP (16)
H A2 D3 L SPHL
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XTHL: Exchange H and L with top of stack

Opcode Operand
XTHL None The contents of the L register are XTHL

exchanged with the stack location
pointed out by the contents of the stack
pointer register. The contents of the H
register are exchanged with the next
stack location (SP+1).
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PUSH: Push the register pair onto the stack
Opcode Operand
PUSH Rp The contents of the register pair PUSH B

designated in the operand are copied
onto the stack in the following
sequence.
1. The SP register is decremented and
the contents of the high order
register (B, D, H) are copied into
that location.
2. The SP register is decremented
again and the contents of the low-
order register (C, E, L) are copied to
that location.
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PUSH Instruction
Registers STACK
SP 23 0008
A
SP 06 0007
B 06 40 C SP 40 0006
D 0005
E
0004
H L 0003
0002
PUSH B
0001
SP <- SP-1
SP <- B ;transfer high order bit to TOS
SP <- SP-1
SP <- C ;transfer low order bit to TOS
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POP : Pop off stack to the register pair
Opcode Operand
POP Rp 1. The contents of the memory POP B

location pointed out by the stack
pointer register are copied to the
low-order register (C, E, L) of the
operand.
2. The stack pointer is incremented by
1 and the contents of that memory
location are copied to the high-
order register (B, D, H) of the
operand.
3. The stack pointer register is again
incremented by 1.
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POP Instruction
Registers STACK
SP 03 0008
A
SP 06 0007
B 06 40 C SP 40 0006
D 0005
E
0004
H L 0003
0002
0001
POP B
C <- SP ; transfer to low order bit from TOS
SP <- SP+1
B <- SP ; transfer to high order bit from TOS

SP <- SP+1
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OUT: Output from Accumulator to 8-bit port address

Opcode Operand
OUT 8-bit The contents of the accumulator are OUT 0AH

port copied into the I/O port specified by the
address operand.
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IN: Input data to accumulator from a port with 8-bit address

Opcode Operand
IN 8-bit The contents of the input port IN 0AH

port address designated in the operand are read and
loaded into the accumulator.
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1 MOV Dst,Src Copy content 1 Byte
2 MVI (R/M), 8-bit Data Load 8-bit to Register/Memory 2 Byte
3 LDA 16-bit address Load Accumulator 3 Byte
4 LDAX Rp(B/D) Load the accumulator indirect 1 Byte
5 LXI Rp, 16-bit Data Load the register pair immediate 3 Byte
6 STA 16-bit address Store Accumulator 3 Byte

7 STAX Rp Store Accumulator Indirect 1 Byte
8 LHLD 16-bit address Load H and L registers direct 3 Byte
9 SHLD 16-bit address Store H and L registers direct 3 Byte
10 XCHG None Exchange H and L with D and E 1 Byte
11 SPHL None Copy H and L registers to the stack pointer 1 Byte
12 XTHL None Exchange H and L with top of stack 1 Byte
13 PUSH Rp Push the register pair onto the stack 1 Byte
14 POP Rp Pop off stack to the register pair 1 Byte
15 OUT 8-bit port address Output from Accumulator to 8-bit port 1 Byte
address
16 IN 8-bit port address Input data to accumulator from a port with 1 Byte
53
8-bit address

E.g. CMA, ADD
E.g. MVI A,32H
E.g. JMP, CALL
54
Arithmetic Instruction
ADD: Add register or memory, to the accumulator

Opcode Operand
ADD R The contents of the operand (register ADD B; A=A + B

M or memory) are added to the ADD M; A = A + M[HL]
contents of the accumulator and the
result is stored in the accumulator.
All flags are modified to reflect the
result of the addition.
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ADC: Add register to the accumulator with carry

Opcode Operand
ADC R The contents of the operand (register ADC B; A = A + B + CY

M or memory) and the Carry flag are ADC M; A = A + M[HL]+CY
added to the contents of the
accumulator and the result is stored
in the accumulator.
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ADC: Add register to the accumulator with carry

Opcode Operand
ADC R The contents of the operand (register ADC B; A = A + B + CY

M or memory) and the Carry flag are ADC M; A = A + M[HL]+CY
added to the contents of the
in the accumulator.
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ADI: Add the immediate to the accumulator

Opcode Operand
ADI 8-bit The 8-bit data (operand) is added to ADI 03; A = A + 03h
data the contents of the accumulator and
the result is stored in the
accumulator.
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ACI: Add the immediate to the accumulator with carry

Opcode Operand
ACI 8-bit The 8-bit data (operand) and the ACI 03; A = A + 03h + CY
data Carry flag are added to the contents
of the accumulator and the result is
stored in the accumulator.
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DAD : Add the register pair to H and L registers

Opcode Operand
DAD Rp The 16-bit contents of the specified DAD B

register pair are added to the
contents of the HL register and the
sum is stored in the HL register.
The contents of the source register
pair are not altered.
If the result is larger than 16 bits, the
CY flag is set. No other flags are
affected.
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DAD Instruction
Registers
A
B 02 08 C
D E +
H 02
04 03
0B L 02 03
04 0B
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SUB : Subtract the register or the memory from the accumulator

Opcode Operand
SUB R The contents of the operand (register SUB B ; A=A-B

M or memory) are subtracted from the SUB M ; A=A-M[HL]
contents of the accumulator, and the
result of the subtraction.
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SBB : Subtract the source and borrow from the accumulator

Opcode Operand
SBB R The contents of the operand (register SBB B; A=A - (B+CY)

M or memory) and the Borrow flag are SBB M; A=A-(M[HL]+CY)
subtracted from the contents of the
accumulator and the result is placed
in the accumulator.
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SUI : Subtract the immediate from the accumulator

Opcode Operand
SUI 8-bit The 8-bit data (operand) is SUI 08h; A = A - 08h

data subtracted from the contents of the
in the accumulator.
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SBI : Subtract the immediate from the accumulator with borrow

Opcode Operand
SBI 8-bit The 8-bit data (operand) and the SBI 08h; A=A - (08h+CY)
data Borrow flag are subtracted from the
contents of the accumulator and the
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INR: Increment the register or the memory by 1

Opcode Operand
INR R The contents of the designated INR B

M register or memory are incremented INR M
by 1 and the result is stored in the
same place.
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INX : Increment register pair by 1

Opcode Operand
INX Rp The contents of the designated register INX D; increments D E

pair is incremented by 1 and the result is
stored in the same place.
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DCR: Decrement the register or the memory by 1

Opcode Operand
DCR R The contents of the designated DCR B

M register or memory are decremented DCR M
by 1 and the result is stored in the
same place.
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DCX: Decrement register pair by 1

Opcode Operand
DCX Rp The contents of the designated register DCX B; decrements BC

pair are decremented by 1 and their DCX D; decrements DE
result is stored at the same place.
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DAA: Decimal adjust accumulator
Opcode Operand
DAA None The contents of the accumulator are DAA

changed from a binary value to two
4-bit BCD digits.
If the value of the low-order 4-bits in
the accumulator is greater than 9 or
if AC flag is set, the instruction adds
6 to the low-order four bits.
If the value of the high-order 4-bits
in the accumulator is greater than 9
or if the Carry flag is set, the
instruction adds 6 to the high-order
four bits.
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DAA Instruction
Registers
1 11
A 2A 0010 1010
B C +0000 0110
D E 0 01 1 0 00 0
H L
Valid BCD number
30
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1 ADD R/M Add register or memory, to the accumulator 1 BYTE
2 ADC R/M Add register to the accumulator with carry 1 BYTE
3 ADI 8-bit data Add the immediate to the accumulator 2 BYTE
4 ACI 8-bit data Add the immediate to the accumulator with carry 2 BYTE
5 DAD Rp Add the register pair to H and L registers 1 BYTE
6 SUB R/M Subtract the register/memory from accumulator 1 BYTE
7 SBB R/M Subtract the source and borrow from accumulator 1 BYTE
8 SUI 8-bit data Subtract the immediate from the accumulator 2 BYTE
9 SBI 8-bit data Subtract immediate from accumulator with borrow 2 BYTE
10 INR R/M Increment the register or the memory by 1 1 BYTE
11 INX Rp Increment register pair by 1 1 BYTE
12 DCR R/M Decrement the register or the memory by 1 1 BYTE
13 DCX Rp Decrement register pair by 1 1 BYTE
14 DAA Decimal adjust accumulator 1 BYTE
72

E.g. CMA, ADD
E.g. MVI A,32H
E.g. JMP, CALL
73
Branching Instructions
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Branching Instruction
JMP: Jump unconditionally

Opcode Operand
JMP 16-bit The program sequence is transferred to JMP 2030H

address the memory address given in the
operand.
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Jump Conditionally
Opcode Operand
JC 16-bit address Jump on Carry, Flag Status: CY=1 JC 2030H

JNC 16-bit address Jump on No Carry, Flag Status: CY=0 JNC 2030H
JZ 16-bit address Jump on Zero, Flag Status: Z=1 JZ 2030H
JNZ 16-bit address Jump on No Zero, Flag Status: Z=0 JNZ 2030H
JP 16-bit address Jump on Positive, Flag Status: S=0 JP 2030H
JM 16-bit address Jump on Minus, Flag Status: S=1 JP 2030H
JPE 16-bit address Jump on Parity Even, JPE 2030H
Flag Status: P=1
JPO 16-bit address Jump on Parity Odd, JPO 2030H
Flag Status: P=0
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CALL Conditionally
Opcode Operand
CC 16-bit address Call on Carry, Flag Status: CY=1 CC 2030H

CNC 16-bit address Call on No Carry, Flag Status: CY=0 CNC 2030H
CZ 16-bit address Call on Zero, Flag Status: Z=1 CZ 2030H
CNZ 16-bit Call on No Zero, Flag Status: Z=0 CNZ 2030H
address
CP 16-bit address Call on Positive, Flag Status: S=0 CP 2030H
CM 16-bit address Call on Minus, Flag Status: S=1 CM 2030H
CPE 16-bit address Call on Parity Even, CPE 2030H
Flag Status: P=1
CPO 16-bit address Call on Parity Odd, CPO 2030H
Flag Status: P=0
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RET: Return from subroutine unconditionally
Opcode Operand
RET 16-bit The program sequence is transferred RET

address from the subroutine to the calling
program.
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Return from Subroutine
Opcode Operand
RC 16-bit address Return on Carry, CY=1 RC 2030H

RNC 16-bit address Return on No Carry, CY=0 RNC 2030H
RZ 16-bit address Return on Zero, Z=1 RZ 2030H
RNZ 16-bit Return on No Zero, Z=0 RNZ 2030H
address
RP 16-bit address Return on Positive, S=0 RP 2030H
RM 16-bit address Return on Minus, S=1 RP 2030H
RPE 16-bit address Return on Parity Even, RPE 2030H
Flag Status: P=1
RPO 16-bit address Return on Parity Odd, RPO 2030H
Flag Status: P=0
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PCHL: Load the program counter with HL contents

Opcode Operand
PCHL None The contents of registers H & L are PCHL

copied into the program counter.
The contents of H are placed as the
high-order byte and the contents of L
as the low-order byte.
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RST : Restart
Opcode Operand
RST 0-7 The RST instruction is used as software RST 5

instructions in a program to transfer the program
execution to one of the following eight locations.
Instruction Restart Address
RST 0 0000H
RST 1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H
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The 8085 has additionally 4 interrupts, which can generate RST instructions
internally and doesnt require any external hardware.

Opcode Operand
TRAP None It restart from address 0024H TRAP

RST 5.5 None It restart from address 002CH RST 5.5
RST 6.5 None It restart from address 0034H RST 6.5
RST 7.5 None It restart from address 003CH RST 7.5
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E.g. CMA, ADD
E.g. MVI A,32H
E.g. JMP, CALL
83
Logical Instructions
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Logical Instruction
CMP: Compare the register or memory with the accumulator

Opcode Operand
CMP R The contents of the operand (register or CMP B

M memory) are compared with the CMP M
contents of the accumulator. Both
contents are preserved. The result of
the comparison is shown by setting the
flags of the PSW as follows:
1. if (A) < (reg/mem): carry flag is set
2. if (A) = (reg/mem): zero flag is set
3. if (A) > (reg/mem): carry and zero
flags are reset
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Logical Instruction
CPI: Compare immediate with the accumulator

Opcode Operand
CPI 8-bit The second byte data is compared CPI 89H

data with the contents of the
accumulator.
The values being compared remain
unchanged. The result of the
comparison is shown by setting the
flags of the PSW as follows:
1. if (A) < data: carry flag is set
2. if (A) = data: zero flag is set
3. if (A) > data: carry and zero flags are
reset
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Logical Instruction
ANA: Logical AND register or memory with the accumulator
Opcode Operand
ANA R M The contents of the accumulator are ANA B

logically ANDed with the contents of the ANA M
operand (register or memory), and the
result is placed in the accumulator.
If the operand is a memory location, its
address is specified by the contents of HL
registers.
S, Z, P are modified to reflect the result of
the operation.
CY is reset. AC is set.
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Logical Instruction
ANI: Logical AND immediate with the accumulator
Opcode Operand
ANI 8-bit The contents of the accumulator are ANI 02H

data logically ANDed with the 8-bit data
(operand) and the result is placed in the
accumulator.
the operation.
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Logical Instruction
XRA: Exclusive OR register or memory with the accumulator
Opcode Operand
XRA R M The contents of the accumulator are XRA B

Exclusive ORed with the contents of the XRA M
registers.
the operation. CY and AC are reset.
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Logical Instruction
XRI: Exclusive OR immediate with the accumulator
Opcode Operand
XRI 8-bit The contents of the accumulator are XRI 02H

accumulator.
the operation.
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Logical Instruction
ORA: Logical OR register or memory with the accumulator
Opcode Operand
ORAR M The contents of the accumulator are ORA B

logically ORed with the contents of the ORA M
registers.
the operation. CY and AC are reset.
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Logical Instruction
ORI: Logical OR immediate with the accumulator
Opcode Operand
ORI 8-bit The contents of the accumulator are ORI 02H

accumulator.
the operation.
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Logical Instruction
RLC: Rotate the accumulator left
Opcode Operand
RLC None Each binary bit of the accumulator is RLC

rotated left by one position.
Bit D7 is placed in the position of D0 as
well as in the Carry flag.
CY is modified according to bit D7.
S, Z, P, AC are not affected.
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Logical Instruction
RLC
A:Accumulator
D7 D6 D5 D4 D3 D2 D1 D0
11 0 1 0 1 0 0 0
0 1 0 1 0 0 0 1
Rotate the accumulator lef CY
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Logical Instruction
RRC: Rotate the accumulator right
Opcode Operand
RRC None Each binary bit of the accumulator is RRC

rotated right by one position.
Bit D0 is placed in the position of D7 as
well as in the Carry flag.
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Logical Instruction
RRC
A:Accumulator
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 0 1 0 0 00
1 0 1 0 1 0 0
Rotate the accumulator right
CY
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Logical Instruction
RAL: Rotate the accumulator left through carry
Opcode Operand
RAL None Each binary bit of the accumulator is RAL

rotated left by one position through the
Carry flag.
Bit D7 is placed in the Carry flag, and the
Carry flag is placed in the least significant
position D0.
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Logical Instruction
RAL
A:Accumulator
D7 D6 D5 D4 D3 D2 D1 D0
11 0 1 0 1 0 0 0
0 1 0 1 0 0 0
CY
0
Rotate the accumulator lef through carry
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Logical Instruction
RAR: Rotate the accumulator right through carry
Opcode Operand
RAR None Each binary bit of the accumulator is RAR

rotated right by one position through the
Carry flag.
Bit D0 is placed in the Carry flag, and the
Carry flag is placed in the most significant
position D7.
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Logical Instruction
RAR
A:Accumulator
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 0 1 0 0 00
1 0 1 0 1 0 0
Rotate the accumulator right through carry
CY
1
100
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Logical Instruction
CMA: Complement accumulator
Opcode Operand
CMA None The contents of the accumulator are CMA

complemented. No flags are affected.
A 2A CMA
0010 1010
1101 0101
D5
101
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Logical Instruction
CMC: Complement Carry
Opcode Operand
CMC None The Carry flag is complemented. No other CMC

flags are affected.
STC: Set Carry

Opcode Operand
STC None The Carry flag is set to 1. No other flags are STC
affected.
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Branch Instructions
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104
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Opcode Operand
NOP None No operation is performed. The NOP

instruction is fetched and decoded.
However no operation is executed.
It is used to increase processing time of
execution.
1 CPU cycle is "wasted" to execute a NOP
instruction
HLT None The CPU finishes executing the current HLT

instruction and stops further execution. An
interrupt or reset is necessary to exit from
the halt state.
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Opcode Operand
DI None The interrupt enable flip-flop is reset and all DI

the interrupts except the TRAP are disabled.
No flags are affected.
EI None The interrupt enable flip-flop is set and all EI
interrupts are enabled.
No flags are affected.
After a system reset or the
acknowledgement of an interrupt, the
interrupt enable flip-flop is reset, thus
disabling the interrupts.
This instruction is necessary to re enable
the interrupts (except TRAP).
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Control Instruction
SIM: Set Interrupt Mask
Opcode Operand
SIM None This is a multipurpose instruction used to : SIM

1. Read the status of interrupts 7.5, 6.5, 5.5
2. Read serial data input bit.
The instruction loads eight bits in the
accumulator with the following
interpretations.
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SIM Instruction
A:Accumulator
D7 D6 D5 D4 D3 D2 D1 D0
SOD SDE X R7.5 MSE M7.5 M6.5 M5.5
Serial Output Data Reset To set mask for RST7.5,RST 6.5, RST5.5
It is used to RST 7.5 if D4=1 Interrupt Masked if bit=1
transmit o/p bits.
Ignored if D6=0
Serial Data Enable
If D6=1; bit D7 is
output to SOD Latch
Mask Set Enable: if 0, bits 0-2 are ignored
if 1, mask is set
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SIM Instruction
A:Accumulator
D7 D6 D5 D4 D3 D2 D1 D0
SOD SDE X R7.5 MSE M7.5 M6.5 M5.5
Example 1: MVI A,08H

SIM
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 1 0 0 0
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Control Instruction
RIM: Read Interrupt Mask
Opcode Operand
RIM None This is a multipurpose instruction used to RIM

read the status of interrupts 7.5, 6.5, 5.5 and
read serial data input bit. The instruction
loads eight bits in the accumulator with the
following interpretations.
A:Accumulator
D7 D6 D5 D4 D3 D2 D1 D0
SID I7 I6 I5 IE 7.5 6.5 5.5
To receive To identify pending interrupts To read interrupt mask

serial data 1=pending interrupt Interrupt Masked if bit=1
0=no pending interrupt Interrupt Enable Flag: 1=enable; 0=disable
110
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SIM and RIM instructions
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Addressing Modes in 8085
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Immediate Addressing Mode
Direct Addressing Mode
Register Addressing Mode
Indirect Addressing Mode
Implicit Addressing Mode
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Immediate Addressing Mode
In this mode, the 8/16-bit data is specified in the instruction itself

as one of its operand.
For example:
MVI B,20H ;means 20H is copied into register B.
LXI D,1034H ;means 1034H is copied into register
pair D.
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Direct Addressing Mode
In this type of addressing mode, the 8 or 16-bit memory address

is directly provided with the instruction.
For example:
LDA 1035H ; here 1035 is 16-bit memory address
IN 8-bit_port_address
OUT 8-bit_port_address
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Register Addressing Mode
This type of addressing mode specifies register or register pair that

contains data.
For example:
MOV A,B ; A <- B
ADD B ; A=A+B
DAD RP ; HL=HL+RP
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Indirect Addressing Mode
In this type of addressing mode, the 16-bit memory address is

indirectly provided with the instruction using a register pair.
For example:
LDAX D; A <- M[DE]
STAX D; A -> M[DE]
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Implicit/Implied Addressing Mode
This mode doesnt require any operand; the data is specified by

the Opcode itself.
For example:
CMP
CMA
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8085
Assembly Language Programs
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Writing Assembly Language Programs
The steps to write Assembly Language Programs are as follows:
Step-1: Read the problem carefully

Step-2: Break it down into small steps
Step-3: Represent these small step in a possible sequence with a flowchart-plan
of attack.
Step-4: Translate each block of flowchart into appropriate mnemonic
instructions.
Step-5: Translate mnemonic into machine code.
Step-6: Enter machine code in memory and execute.
Step-7: Start troubleshooting-Debugging a program
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Documentation
Appropriate comments are critical for conveying the logic behind
the program.
The comment should explain what is intended; they should not
explain mnemonics.
Comment is optional.
Example:
MOV A,B ; Move data from B to A
MOV A,B ; send data to accumulator for I/O processing
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Program Execution
Machine code can be loaded in R/W memory, with reference to
starting memory location.
Execution can be done in two ways:
1. Execute entire code on click
2. Single step execution
It will execute one instruction at a time.
We can observe the content of register and flag after execution of each
instruction.
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Debugging Program
Debug a program is similar to troubleshooting hardware.
In program, result is generally binary: either it works or it doesnt.
If the code doesnt work, it is essential to search carefully for
errors in programming logic, machine codes and execution.
How to Debug machine code:
Translating assembly to machine code is similar to building a
circuit.
Following errors are common:
1. Selecting a wrong code
2. Specifying the wrong jump location
3. Writing memory address in decimal, thus specifying wrong jump location
4. Writing lower order and higher order bits in wrong sequence.
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Adding Two 8-bit Numbers
Write a program to add data at 1005H &
1006H memory location and store the result at Start
1007H memory location.
Transfer 16-bit
address to HL Pair
1. LXI H,1005 ; to retrive m/m addr
2. MOV A,M ; retrieve m/m content Data Transfer:A <- M[HL]
3. INX H ;increment memeory to 1006H
HL=HL + 1
4. ADD M;add accumulator with M[1006]
5. STA 1007 A = A + M[HL]
6. HLT ; HLT program
Store result
[1007] <- A
End
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Assembly Language
Language Basics
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8085 Assembly Program
Write a program to load register B with 37H and display number at
the output Port 01
MVI B,37; B <- 37H
MOV A,B ; A <- B for I/O processing
OUT 01 ; PORT 01 <- A
HLT
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Language Basics
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Timing Cycle required by 8085 Instruction
Operation T-States
Opcode Fetch 4-6T
Operand Fetch 3T
Memory Read 3T
Memory Write 3T
I/O Read 3T
I/O Write 3T
Instruction that require 5T-States for Opcode Fetch

HLT
Instructions that require 6T-States for Opcode Fetch
1. CALL 5. PCHL
2. Conditional CALL 6. SPHL
3. DCX 7. PUSH
4. INX 8. Conditional RET
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Unit-4
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Language Basics
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Machine Cycle required by 8085 Instruction
Operation M/C
Fetch (F) 1
Memory Read (MEMR) 1
Memory Write (MEMW) 1
I/O Read (IOR) 1
I/O Write (IOW) 1
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Timing and Machine Cycle
1. MOV B , D
Machine Cycle:
1(F)= 1 Machine Cycle
Timing Cycle:
= 4T(Opcode Fetch)
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2. MVI C ,17H
Machine Cycle: Fetch + Read Immediate data (MEMR)

1 + 1=2
Timing Cycle: Opcode Fetch + MEMR

4T + 3T= 7T
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3. MVI M , 25H
Machine Cycle: Fetch + Read data (MEMR)+Write data(MEMW)

1 + 1 +1=3
Timing Cycle: Opcode Fetch + MEMR + MEMW

4T + 3T + 3T = 10T
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4. MOV A,M
Machine Cycle: Fetch + Read Memory(MEMR)

1 + 1 =2

4T + 3T = 7T
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4. MOV M, A
Machine Cycle: Fetch + Write Memory(MEMW)

1 + 1 =2
Timing Cycle: Opcode Fetch + MEMW

4T + 3T = 7T
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5. NOP
Machine Cycle: Fetch

= 1 M/C Cycle
Timing Cycle: Opcode Fetch
= 4T
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6. HLT : Halt and enter wait state

= 1 or more M/C Cycle
Timing Cycle: Opcode Fetch
= 5T or more T-States
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7. IN 18H
Machine Cycle: Fetch + MEMR + IOR

=1 +1+1
=3
Timing Cycle: Opcode Fetch + MEMR + IOR
= 4T + 3T + 3T
= 10T
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8. OUT 19H
Machine Cycle: Fetch + MEMR + IOW

=1 +1+1
=3
Timing Cycle: Opcode Fetch + MEMR + IOR
= 4T + 3T + 3T
= 10T
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9. ADD B
= 1 Machine Cycle
Timing Cycle:
= 4T(Opcode Fetch)
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10. ADI 26H

1 + 1=2

4T + 3T= 7T
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11. ADD M
Machine Cycle: Fetch + MEMR

1 + 1=2

4T + 3T= 7T
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12. SUB C

= 1 Machine Cycle
Timing Cycle:
= 4T(Opcode Fetch)
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13. SUI 26H

1 + 1=2

4T + 3T= 7T
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14. SUB M
Machine Cycle: Fetch + MEMR

1 + 1=2

4T + 3T= 7T
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15. LDA 2030H
Machine Cycle: Fetch + ReadL 8-bit + ReadH 8-bit +MEMR (content)

=1 +1+1+1
=4
Timing Cycle: Opcode Fetch + MEMR + MEMR + MEMR
= 4T + 3T + 3T + 3T
= 13T
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16. POP RP : POP B
Machine Cycle: Fetch + MEMR (SP) + MEMR (SP+1)

=1 +1+1
=3
Timing Cycle: Opcode Fetch + MEMR + MEMR
= 4T + 3T + 3T
= 10T
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16. PUSH RP : PUSH B
Machine Cycle: Fetch + MEMW (SP) + MEMW (SP-1)

=1 +1+1
=3
= 6T + 3T + 3T
= 12T
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LHLD Instruction
Registers Memory
02 0001
A
04 0002
B C 0A 0003
06 0004
D E
0F 0005
H L 0D 0006
05 0007
03 0008
LHLD 0006H
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17. LHLD 2034H
Machine Cycle: Fetch + MEMR_L(2034) + MEMR_H(2034)

+ MEMR_Content(2034,SP+1)
+ MEMR_Content (2035)
=1 +1+1+1+1
=5
Timing Cycle: Opcode Fetch+ MEMR + MEMR + MEMR + MEMR
= 4T + 3T + 3T + 3T + 3T
= 16T
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12. RAR

= 1 Machine Cycle
Timing Cycle:
= 4T(Opcode Fetch)
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18. XTHL
Machine Cycle: Fetch + MEMR(SP)+MEMW(L)+

MEMR(SP+1)+MEMW(H)
=1 +1+1+1+1
=5
Timing Cycle: Opcode Fetch+ MEMR + MEMW + MEMR + MEMW
= 4T + 3T + 3T + 3T + 3T
= 16T
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19. CALL 2030H
Machine Cycle: Fetch + MEMW_L(Store) + MEMW_H(Store)

+ MEMR_L(Call) + MEMR_H(Call)
=1 +1+1+1+1
=5
Timing Cycle: Opcode Fetch+ MEMW + MEMW + MEMR + MEMR
= 6T + 3T + 3T + 3T + 3T
= 18T
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20. RET
Machine Cycle: Fetch + MEMR (SP) + MEMR (SP+1)

=1 +1+1
=3
= 4T + 3T + 3T
= 10T
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Assembly Language
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Find Timing Cycle, Machine Cycle and Byte Size of following Instructions
1. LDAX B
2. SHLD 2470
3. SPHL
4. DAA
5. INR R/M
6. JMP
7. PCHL
8. CMP R/M
9. RRC
10. RIM
11. SIM
12. ORA R/M
13. XCHG
14. DI
15. EI
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Sr. No. Instruction Byte Size Machine Cycle T-States
1. LDAX B 1 F+R=2 4T+3T=7T
2. SHLD 2470 3 F+R+R+W+W=5 4T+3T+3T+3T+3T=16T
3. SPHL 1 F=1 =6T
4. DAA 1 F=1 =4T
5. INR R 1 F=1 =4T
INR M 1 F+R+W=3 4T+3T+3T=10T
6. JMP 2030 3 F+R+R=3 4T+3T+3T=10T
7. PCHL 1 F=1 =6T
8. CMP R 1 F=1 =4T
CMP M 1 F+R=2 4T+3T=7T
9. RRC 1 F=1 =4T
10. RIM 1 F=1 =4T
Sr. No. Instruction Byte Size Machine Cycle T-States
11. SIM 1 F=1 =4T
12. ORA R 1 F=1 =4T
ORA M 1 F+R=2 4T+3T=7T
13. XCHG 1 F=1 =4T
14. DI 1 F=1 =4T
15. EI 1 F=1 =4T
154
Assignment 3: Unit 4
1. Differentiate the following
i. Assembly Language and Machine Language
ii. Differentiate JMP , CALL and RET instruction
2. What is an Assembler? Is Assembly Language portable?
3. Explain following types of interrupt:
i. Level triggered and edge triggered Interrupt
ii. Vectored and Non vectored Interrupt
iii. Maskable and non-maskable Interrupt
4. What does 2nd byte in IN and OUT instruction specifies?
5. Draw and explain PSW in 8085.
6. Explain RIM and SIM Control Instructions.
7. What will happen if HLT instruction is executed in processor?
Unit-4
Unit-4 Assembly
Assembly Language
Language Basics
Basics 155 Darshan
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Unit-4

Assembly Language Basics

Machine Independent High Level Language High Level Language

Compiler Assembly Language

Compilers translate high-level programs translates

A statement in a high-level language is translated

Assembly Language: Machine Language:

Source Object Executable

A project may consist of multiple source files

Based on Byte Size Based on Function

Logic & Bit Manipulation

Based on Byte Size Based on Function

Logic & Bit Manipulation

Instruction Binary Code Hexa Code

Based on Byte Size Based on Function

Logic & Bit Manipulation

IN 0AH 1101 1011 DB: 1st Byte

Based on Byte Size Based on Function

Logic & Bit Manipulation

Instruction Binary Code Hexa Code

Based on Byte Size Based on Function

Data Transfer Instructions

Instruction Description Example

MOV R d, R s This instruction copies the contents MOV B, C

Instruction Description Example

MVI M, Data The 8-bit data is stored in the MVI B, 57H

Instruction Description Example

LDA 16-bit The contents of a memory location, LDA 2050H

Instruction Description Example

LDAX Rp The contents of a memory location, MVI B,00H

Instruction Description Example

Instruction Description Example

Instruction Description Example

STAX Rp The contents of the accumulator are STAX B

Instruction Description Example

LHLD 16-bit The instruction copies the contents LHLD 2050H

Instruction Description Example

SHLD 16-bit The contents of register L are stored in SHLD 0002H

Instruction Description Example

XCHG None The contents of register H are XCHG

Instruction Description Example

SPHL None The instruction loads the contents of the SPHL

Instruction Description Example

XTHL None The contents of the L register are XTHL

PUSH Rp The contents of the register pair PUSH B

POP Rp 1. The contents of the memory POP B

B <- SP ; transfer to high order bit from TOS

Instruction Description Example

OUT 8-bit The contents of the accumulator are OUT 0AH

Instruction Description Example

IN 8-bit The contents of the input port IN 0AH

6 STA 16-bit address Store Accumulator 3 Byte

Based on Byte Size Based on Function

Instruction Description Example

ADD R The contents of the operand (register ADD B; A=A + B

Instruction Description Example

ADC R The contents of the operand (register ADC B; A = A + B + CY

Instruction Description Example

ADC R The contents of the operand (register ADC B; A = A + B + CY

Instruction Description Example

Instruction Description Example

Instruction Description Example

DAD Rp The 16-bit contents of the specified DAD B