Case Study

Mobile Phone
ARMS Micro Controller

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 Mobile phone SoC (System-on-Chip)
Hardware units
Microcontroller or ASIP (Application Specific
Instruction Set Processor) to process encoding and

deciphering and another ASIP for voice

compression.

ASIC for the actions of dialing,

modulating, demodulating, interfacing
the key board interfacing and multiple
line LCD matrix displays, stores data
input and recalls data from memory.
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 Mobile phone SoC (System-on-Chip)
Hardware units
DSP core, CCDSP, DSP, video, voice and
Pixel Processors
Flash, EEPROMs and SRAMs,
Peripheral circuits, ADC, DAC and
Interrupt controller
Direct Memory Access controller
LCD controller
Battery

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 Mobile Phone Embedded Software
components development tools
Mobile phone software development
tools are as follows:
RTOS Windows Mobile, Palm OS, or
Symbian, BREW
Java 2 Micro Edition (J2ME) along with
KVM as a Java Virtual Machine
(Java Wireless toolkit with JDK (Java
Development kit)

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 Software components

Mobile browser for access the Web

Down-loader for Java games,

ringtones, games, wall papers

Simple camera with Bluetooth

synchronization, IrDA and WAP
connections support
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 Set of Robots

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 Set of Robots
Diagrammatic representation

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 Master Robot Functions

1. It receives from a remote controller

commands to start the music, stop
the music and the code for the
specific orchestra to be played.

2. It sends the PWM signals to the

ports for the moving the sticks in
both hands as per the program.
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 Master Robot Functions

3. It establishes and binds the sockets

(the virtual devices) connection with the
slaves.
It sends the signals through sockets
using IrDA protocols. The byte
streams response to the clients are
as per the music file being played .

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 Slave Robot Functions

1. It establishes and binds the sockets

(the virtual devices) connection
with the master.

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 Slave Robot Functions

2. It receives from a master socket the

commands accept ( ) and write ( )
from the master. It receives
commands from master to start the
music, stop the music and the code
for the specific orchestra tobe
played.

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 Slave Robot Functions

3. It receives the signals through

sockets using IrDA protocols. The
byte streams from the server re as
per the music file being played.

4. Slave robots speaker outputs for

playing the music.

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 Robot Hardware units
1. Microcontroller or ASIP
2. Music file processor
3. RAM for storing temporary variables and
stack
4. ROM for application codes and RTOS codes
for scheduling the robot actions and tasks
5. Timer, Flash memory for storing user
preferences and music files.
6. IrDA controller (Section 3.10.3)
7. Direct Memory Access controller
8. Power supply source or battery
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 End of case

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 VANCED PROCESSOR ARCHITECTURES
AND MEMORY ORGANISATION

ARM
A Mobile phone system popular
architecture processors

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 ARM Features
1. ARM has 32-bit architecture but
supports 16 bit or 8 bit data types also.
2. ARM is programmable as little endian
or big endian data alignment in
memory.
3. ARM provides the advantage of using a
CISC in terms of functionality, along
with the advantage of an RISC in terms
of faster program implementation as
well as reduced code lengths.
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 ARM Features
ARM7, ARM9 and ARM 11 microprocessors

1. ARM processor has an RISC core for

processing

2. Combination of RISC and CISC features-

ARM supports to a complex addressing
modes based instruction set

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 In-built compilation unit
Compiles the CISC instructions into RISC
formats, which are then implemented by
the RISC core of the processor.

Internally the implementation for many

instructions is like in an RISC (without the
micro-programmed unit)
Jazelle technology
Faster Java codes execution
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 ARM Thumb 16-bit instructions
Thumb Set designed for 16-bit word lengths and
instructions, which internally executes by same 32-
bit core.
Instruction fetch of 2 bytes in Thumb mode in
place of 4 bytes in ARM mode.
Data alignment at steps of 2 bytes in Thumb mode
in place of 4 bytes in ARM mode Memory savings
of up to 35%, over the equivalent 32-bit code,
while retaining all the benefits of a 32-bit system
(such as access to a full 32-bit address space).
Enables 32-bit performance at the 8/16-bit system
cost in terms of memory needs.

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 Thumb and 32-bit ARM modes
Switch from one mode to another
No overheads (in terms of time and memory)
in moving between Thumb and the
normal ARM state of the codes. Two
states are compatible on a normal
basis.
Gives code designer complete control
over performance and code-size
optimisation

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 ARM7 versions
ARM7TDMI (Integer Core)
ARM7TDMI-S, (Synthesisable version of ARM7TDMI)
ARM7EJ-S (Synthesisable core with DSP and Jazelle
technology)
ARM720T (cached processor macrocell ,
8K Cached Core with Memory Management
Unit(MMU) supporting operating systems1
including Windows CE, Palm OS, Symbian OS
and Linux)
130 MIPS using Dhrystone 2.1 benchmark in
typical 0.13m process
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 ARM9 versions
ARM920T (Dual 16k caches with MMU
support multiple OSs.
ARM922T (Dual 8k caches for applications
support multiple OSs1.
ARM940T (Dual 4k caches for embedded
control applications running a RTOS) 32-bit
RISC processor core Super scaling 5-stage
integer pipeline. 8-entry write buffers to
avoid blocking the processor on external
memory writes
Achieves 1.1 MIPS/MHz, 300 MIPS
(Dhrystone2.1) in a typical 0.13m process
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 ARM11 versions
Families with ARMv6 instruction set
architecture that includes the Thumb
extensions for code density, Jazelle
technology for Java acceleration, ARM DSP
extensions, and SIMD media processing
extensions. MMU) supporting operating
systems1 and palm OS
32-bit RISC processor core with 8-stage integer
pipeline, static and dynamic branch prediction,
and separate load-store and arithmetic
pipelines to maximize instruction throughput
Targets a performance range of Dhrystone
MIPS
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 Memory Architecture

ARM7 has Princeton memory architecture.

ARM9 processor has Harvard architecture

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Faster implementation and Reduced code
lengths
Due to the instant availability of the register
word to the execution-unit.
Reduced code lengths Most instructions
use registers as operands.
Few bits in the instruction specify a register
as operand. 8, 16 or 32 bits specify a
memory address as operand and the
displacement bits in the instruction.

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 ARM registers
R0 to R15.
R15 also function as program
counter.
R14 function as link register.
R13 may be used as stack pointer
CPSR (current program status register)
SPSR (saved program status register).

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 ARM Architecture

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 ARM Processor
End of Unit

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 AVANCED PROCESSOR ARCHITECTURES
AND MEMORY ORGANISATION

SHARC and TigerSHARC

Super Harvard Single-
Chip Computer(SHARC)
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 SHARC
Processor from Analog Devices.
Super Harvard architecture means more
than one set of address and data buses for data
For example,
set J of address and data buses for data-
memory space,
set K of address and data buses for data-
memory space, and
set I of address and data buses for program
memory space
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 SHARC functions
Program memory configurable as
program and data memory parts (Princeton
architecture)
SHARC functions as VLIW (very large
instruction word) processor.
used in large number of DSP
applications.
Controlled power dissipation in floating
point ALU.
Different SHARCs can link by serial
communication between them
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 SHARC functions
ON chip memory 1 MB Program
memory and data memory (Harvard
architecture)
External OFF chip memory
OFF chip as well as ON-chip Memory
can be confirgured for 32-bit or 48 bit
words.

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 TigerSHARC
Highest performance density family of
processors from Analog Devices
Precision high-performance integrated
circuits used in analog and digital signal
processing applications
designed for multiprocessing
applications and for peak performance
greater than BFLOPS (billion floating-point
operations per second)

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 Example
A DSP-TS203SABP-050 processor
processes using 250 MHz clock and on
chip memory of 6 M bits and operates at
1.2V/3.3 V
Low voltage design helps in processing
with little power dissipation.
Analog Devices claims the highest
performance per Watt.

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 Tiger SHARC
MultipleTiger SHARCs can connect by
serial communication at 1 GB ps.
A TigerSHARC version has 24 M bits ON-
chip memory.
Two ALUs and twos set of address and
data buses for data memory
On set of address and data buses for
program memory
TigerSHARC is available as IP core also
so that new applications and
enhancements can be developed.
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 Tiger SHARC

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