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TO VLSI
From
1945
ENIAC filled an entire room!
17,468 vacuum tubes,
70,000 resistors, and
10,000 capacitors
6,000 manual switches
and many blinking lights!
Could add 5,000 numbers in
a single second
To
1947
Point-contact transistor
1954
first computer with no tube
800 transistors and
10,000 germanium crystal rectifiers
only 100 watts
1958
Invention of the Integrated Circuit
1958
A device having multiple electrical components and their
interconnects manufactured on a single substrate
And To
this:
Magnified
Some packages
Why Integrated Circuits?
• pMOS
• nMOS
• CMOS
• BiCMOS
nMOS transistor structure
Basic MOS Transistors
• Minimum line width
• Transistor cross section
• Charge inversion channel
• Source connected to substrate
• Enhancement vs Depletion mode devices
• pMOS are 2.5 time slower than nMOS due
to electron and hole mobilities
MOSFET Operation
MOSFET Operation
MOSFET Operation
MOSFET Operation
Gate voltage and the channel
gate
current
source drain Vds < Vgs - Vt
Id
gate
current
source drain Vds = Vgs - Vt
Id
gate
source drain
Vds > Vgs - Vt
Id
nMOS transistor
pMOS transistor
CMOS Technology
• First proposed in the 1960s. Was not seriously considered until the
severe limitations in power density and dissipation occurred in
NMOS circuits
• Now the dominant technology in IC manufacturing
• Employs both pMOS and nMOS transistors to form logic elements
• The advantage of CMOS is that its logic elements draw significant
current only during the transition from one state to another and
very little current between transitions - hence power is conserved.
• In the case of an inverter, in either logic state one of the transistors
is off. Since the transistors are in series, (~ no) current flows.
CMOS transistor
A
GND VDD
Y SiO2
n+ diffusion
p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1
p substrate
Oxidation
SiO2
p substrate
Photoresist
• Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light
Photoresist
SiO2
p substrate
Lithography
Photoresist
SiO2
p substrate
Etching
Photoresist
SiO2
p substrate
Strip Photoresist
SiO2
p substrate
n-well
• n-well is formed with diffusion or ion implantation
• Diffusion
– Place wafer in furnace with dopant gas
– Heat until dopant atoms diffuse into exposed Si
• Ion Implantation
– Blast wafer with beam of dopant ions
– Ions blocked by SiO2, only enter exposed Si
SiO2
n well
Strip Oxide
n well
p substrate
Polysilicon
• Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers)
• Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor
Polysilicon
Thin gate oxide
n well
p substrate
Polysilicon Patterning
• Use same lithography process to pattern
polysilicon
Polysilicon
Polysilicon
Thin gate oxide
n well
p substrate
N-diffusion
• Pattern oxide and form n+ regions
• Self-aligned process where gate blocks diffusion
• Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
n+ Diffusion
n well
p substrate
N-diffusion cont.
n+ n+ n+
n well
p substrate
N-diffusion cont.
n+ n+ n+
n well
p substrate
P-Diffusion
• Similar set of steps form p+ diffusion
regions for pMOS source and drain and
substrate contact
p+ Diffusion
p+ n+ n+ p+ p+ n+
n well
p substrate
Contacts
• Now we need to wire together the devices
• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed
Contact
n well
p substrate
Metallization
• Sputter on aluminum over whole wafer
• Pattern to remove excess metal, leaving wires
Metal
Metal
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate
Fabrication, Testing & Packaging
Final IC After Packaging
Wafer Processing
direction of pull and rotation
crystal holder
• Czochralski process
seed
– Melt silicon at 1425 degrees C growing crystal (ingot)
– Add impurities to dope crystal
– Spin and gradually extract seed crystal
molten silicon
Natural oxide: silicon will readily grow an oxide (5-10nm) if exposed to oxygen in the air!
The range for useful oxide thickness: 25nm (MOS gates) - 1500nm (field oxide)
Dry oxidation
Si + O2 SiO2 (900-1200°C)
O2
700nm oxide: 10hours (1200°C)
SiO2
Good oxide quality: gate oxide
Silicon
Wet oxidation (water vapor or steam)
Si + H2O SiO2 + 2H2 (900-1200°C)
700nm oxide: 0.65hours (1200°C)
Poor oxide quality: field oxide
IMPLANTATION/DIFFUSION