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Design
Emre Yengel
Fall 2014
Introduction
• Sequential circuit
o Output depends not just on present inputs (as in combinational
circuit), but on past sequence of inputs
• Stores bits, also known as having “state”
o Simple example: a circuit that counts up in binary
Inputs Outputs
COMBINATIONAL
LOGIC
Current State
Next state
Registers
Q D
CLK
• A sequential circuit consists of a feedback path, and employs some memory
elements.
Introduction
• Flight attendant call button Call Blue light
Memory Q
command element stored value
clock
t Register
tsu thold D Q
D DATA CLK
STABLE t
tc 2 q
Q DATA
STABLE t
Latch Register
stores data when stores data when
clock is low or high clock rises
D Q D Q
Clk Clk
Clk Clk
D D
Q Q
Latches
Static Latches and Registers:
Bistability Principle
V o1 Vi2
V i1 V o2
A
When the gain of the inverter in the
V i 2 = V o1
transient region is larger than 1, only A
and B are stable operation points, and C is C
a metastable operation point.
B
V i 1 = V o2
Bistability Principle
R (reset)
S=0 S=0 S=1 S=0
t t t t Recall…
1 1 0 0 0
0 0 1 1 1
0
1
1 1 0 0 0
0 Q 0 Q 1 1 X
Q Q
1
S
0
R1
0 a
t 1
0
1
Q
0
SR Latches
Characteristics table for active-high input S-R latch (also
known as NOR gate latch):
S R Q Q'
0 0 NC NC No change. Latch
remained in present state. S Q
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET. R Q'
1 1 0 0 Invalid condition.
1
Q may oscillate. Then, because one path will be t
0
slightly longer than the other, Q will eventually 1
settle to 1 or 0 – but we don’t know which. Q
0
SR Latches
Y R
...S1R1 never = 11
Clock Signals of a Latch
1 C Q
C
0
D latch symbol
1
S
0
1
R
0
1
Q
0
Problem with Level-Sensitive D Latch
• D latch still has problem (as does SR latch)
▫ When C=1, through how many latches will a signal
travel?
▫ Depends on for how long C=1
Clk_A -- signal may travel through multiple latches
Clk_B -- signal may travel through fewer latches
▫ Hard to pick C that is just the right length
Can we design bit storage that only stores a value on the
rising edge of a clock signal?
Y D1 Q1 D2 Q2 D3 Q3 D4 Q4 Clk
C1 C2 C3 C4
Clk
Clk_A Clk_B
Flip-Flop
• Flip-flop: Bit storage that stores on clock edge, not level rising edges
• One design -- master-servant Clk
▫ Two latches, output of first goes to input of second, master
latch has inverted clock signal
Note:
▫ So master loaded when C=0, then servant when C=1 Hundreds of
▫ When C changes from 0 to 1, master disabled, servant loaded different flip-
flop designs
with value that was at D just before C changed -- i.e., value at exist
D during rising edge of C
D flip-flop
D latch D latch
D Q’
Dm Qm Ds Qs’
Q
Cm Cs Qs
master servant
Clk
Edge-Triggered Flip-Flops
S-R, D and J-K edge-triggered flip-flops. Note
the “>” symbol at the clock input.
S Q D Q J Q
C C C
R Q' Q' K Q'
S Q D Q J Q
C C C
R Q' Q' K Q'
CLK CLK
CLK' CLK'
CLK* CLK*
Y D1 Q1 D2 Q2 D3 Q3 D4 Q4
Two latches inside
each flip-flop
Clk
Clk_A Clk_B
D-Latch vs. D-Flip-Flop
CLK
Q'
X
Combinational Y D Q Q2 = Y*
logic circuit
Z CLK
Q'
D Q Q3 = Z*
Transfer CLK
Q'
J
Q
Pulse
CLK transition
detector
Q'
K
J-K flip-flop.
J-K Flip-Flop
J-K flip-flop.
J
Q
Pulse
CLK transition
detector
Q'
K
Characteristic
T CLK
table.
Q(t+1) Comments Q T Q(t+1)
0 Q(t) No change 0 0 0
1 Q(t)' Toggle 0 1 1
1 0 1
1 1 0
Q(t+1) = T.Q' + T'.Q
Summary
SR latch Level-sensitive SR latch D latch D flip-flop
S (set) S D
S1 S D latch D latch
D Q’
DmQm Ds Qs’
C C Q
Cm Cs Qs
Q Q Q master servant
R
R1 R Clk
R (reset)
Feature: S=1 sets Feature: S and R only Feature: SR can’t be 11 if Feature: Only loads D value
Q to 1, R=1 resets have effect when C=1. D is stable before and present at rising clock edge, so
Q to 0. Problem: We can design outside while C=1, and will be 11 values can’t propagate to other
SR=11 yield circuit so SR=11 never for only a brief glitch even flip-flops during same clock
undefined Q. happens when C=1. if D changes while C=1. cycle. Tradeoff: uses more
Problem: avoiding SR=11 Problem: C=1 too long gates internally than D latch,
can be a burden. propagates new values and requires more external
through too many latches: gates than SR – but gate count
too short may not enable a is less of an issue today.
store.