Verilog HDL

Presentation by
Rakesh Paladugula.
 Verilog, standardized as IEEE 1364, is a hardware description
language (HDL) used to model electronic systems. It is most commonly used in
the design of digital circuits at the register-transfer level(RTL)of abstraction. It is
also used in the verification of analog circuits and mixed-signal circuits.

It was created by Prabhu Goel, Phil Moorby , Chi-Lai Huang and

Douglas Warmke between late 1983 and early 1984.
History:
• Verilog-95 : IEEE Standard 1364-1995
Cadence transferred Verilog into the public domain under
t the Open Verilog International (OVI) (now known as Accellera) organization
• Verilog-2001 : IEEE Standard 1364-2001
• Verilog-2005 : IEEE Standard 1364-2005
• System Verilog : IEEE standard 1800-2012(current version)
Verilog Simulators(Popular):
• Riviera-PRO by ALDEC
• ISE Simulator by XILINX
• ModelSim and Questa by MENTOR GRAPHICS
• Quartus II(Qsim) by ALTERA
• Verilog-XL by CADENCE DESIGN SYSTEMS
• Vivado Simulator by XILINX
Contents:
• Abstraction Levels
• One bit half adder code – (All Styles)
• Data Types
• Vectors,Numbers,Arrays,Parameters
• Operators
• Verilog Processes
• Initial,always
• Procedural Assignments
• Delays in continuos concurrent Assignments
• Begin_end,fork_join
• Timing control statements
• Branching Constructs
• Loops
• Task and Function
• System Tasks
• Compiler Directives
• References
Abstraction Levels: (Different ways to write RTL code)
• Structural Level: Primitives and modules that are ready to be
instantiated
eg: and,or,not,buf,xor,nand,nor,xnor,bufif1,bufif0
Syntax: Primitive_name Instance_name(output,input,input);
eg: nand n1(y,a,b);

• Data Flow Level: Signals are assigned through the data manipulating
instructions
eg: y = !(a & b);
• Behavioral Level:
Highest Level of design description
Function only
eg: Multiplexer

always@(a,b,sel) a

2x1 Mux
begin
if(sel == 0) b out
out = a;
else
out = b;
end sel
Register Transfer Level(RTL) modelling style:
• An RTL modelling is a Synthesizable coding style
• It is widely used in Synchronous designs that involves both
combinational and sequential design
• RTL style basically represents the dataflow between Registers
Half Adder implementation using different styles:
• Gate Level Modelling

module half_adder(input a,b, output sum,carry);

xor(sum,a,b);
And(carry,a,b);

endmodule
• Data Flow Modelling:

module half_adder(input a,b, output sum,carry);

assign sum = a^b;

assign carry = a &b;

endmodule
• Behavioral modelling:
module half_adder(input a,b, output sum,carry);
always@(a,b)
begin
case({a,b})
2’b00: begin
sum = 0 ; carry = 0;
end
2’b10: begin
sum = 1 ; carry = 0;
end
2’b01: begin
sum = 1 ; carry = 0;
end
2’b11: begin
sum = 0 ; carry = 1;
end
Data Types:
• Net
• Reg
• Integer
• Real
• Time
• Nets –(net data type)
1. Nets are continuously driven by combinational logic
2. They represent physical connection between components

Declaration:
wire A,B,Y;
assign Y = A & B;

Wire elements are used as inputs and outputs in module declaration

Wire elements are only legal type on L.H.S of assign statement
• Regs – (reg data type)
values retained until updated

Declaration:
reg a,b;

reg elements are only legal type on L.H.S of procedural

block(always,initial)
reg cannot be used in L.H.S of assign statement
• Integer Data type:
It is of 32-bit size
Integers store values as signed quantities
suitable for counting and number calculations
Syntax:
integer x,y;

• Real Data type:

Allows decimal and scientific notation

Syntax:
real x,y;
Time Data type:
• For storing and manipulating simulation time quantities
• Stores simulation time
• It is of size 64-bit

Syntax:
time x,y;
Default values of data-types
• Wire : High Impedance “z”
• Reg : Unknown value “x”
• Integer : Unknown value “x”
• Real : 0.0
• Time : Unknown value “x”
Vectors:
• Represents Buses

Eg: reg [3:0] x;

x[3]
x x[2]
x[1]
x[0]
Numbers:
• <size>’<base><number>

• Binary – b or B eg: 4’b1 = 1111

• Decimal – d or D eg: 4’d1 = 0001
• Hexadecimal – h or H eg: 8’h72 = 0111_0010
• Octal –o or O eg: 6’o23 = 010_011
Fixed Sized Arrays:
• reg my_reg [0:5] //Declares an array of 6, 1-bit registers
• reg arrayb[7:0][0:255] //Declares a two dimensional array of 1-bit
registers
• Integer inta[1:64] //Declares an array of 64 integer values

Register Assignments:

reg my_reg[0:5]
my_reg[2] = 1’b1; //Assigns 1 to 3rd element of array
Memories:
• A one dimensional array with elements of type reg
• Used to model ROMs,RAM and reg files

Eg: reg [7:0]mem[0:255] //Declares a memory mem of 256 8-bit

Parameters:
• Parameters are not variables , they are constants, their value can’t be
changed during run_time
Eg:
module ram(clk,reset,din,r_add,w_add,dout)
parameter dt_width = 8;
parameter ad_depth = 256;
-------------------------
reg [(dt_width-1):0]mem[(ad_depth-1):0]
endmodule
Limitations:
parameters can’t be declared outside module
Strings:
• A string is a sequence of characters enclosed by double quotes(‘’’)
and contained on a single line
• 8-bit ASCII value represents a character
Eg:
module string_check();
reg [8*6:1]string_reg;
initial
begin
string_reg = “RAKESH”;
$display(“name = %s”,string_reg);
end
endmodule
Operators:
• Logical operators
• Bitwise operators
• Shift operators
• Concatenation operators
• Relational operators
• Equality operators
• Conditional operators
• Arithmetic operators
Logical Operators
• AND (&& ),OR (||),NOT( !)
• Evaluates to a single bit value (1- True,0-False, X-Unknown)

Eg: a= 5,b=7
y = a && b;
Sol: y = 1 //because a and b are not equal to zero
Bitwise Operators:
• AND (&),OR(|),XOR(^),NEGATION(~),XNOR(~^)

Eg: a=5,b=7
y = a & b;

SOL: a = 1 0 1
b=111
y= 101
Shift Operators:
• Shift Right (>>), Shift left (<<)

Eg:
a = 2;
y = a >> 2;
SOL: initially a = 0 1 0;
after right shift a = 0 0 1;
therefore y = 1; //After Shift
Relational Operators:
• > , < , <= , >=

Eg:
a =4,b=3;
a >= b //Evaluates to 1
a<= b // Evaluates to 0
Equality Operators:
• Logical == , !=

• Eg:
a=4,b=4
a == b //Evaluates to 1
a ! = b // Evaluates to 0
Conditional Operators:
• Condition_expression ? True_expression : false expression

Eg:
a=2
y = a ? 3 : 4;
Output:
y = 3 //because a not equal to ‘0’
Arithmetic Operators:
• Multiplication [*]
• Division [/]
• Subtract [-]
• Add [+]
• Modulus [%]
Verilog Processes:
• Continuous Concurrent assignments
• Procedural Assignments

Continuous Concurrent assignments:

Assigns values to nets
The Assignments occurs whenever the value of R.H.S changes

Eg: wire y;
assign y = a^b;
Procedural Assignments:
• Update values of variables under control of procedural flow
constructs that surround them

begin
if(sel == 0)
z = a; // Z must be reg type
else
z = b;
end
Initial:
• Execution starts at simulation time
• Once executable only

Initial
begin
reset = 1’b1;
#10 reset = 1’b0;
end // Execution stops when the last statement executed
always:
• Repeats continuously through out during simulation

always
begin
//procedural statements and assignments
end

Application:
used to generate infinite signal (clock)
Asynchronous and synchronous reset:
Asynchronous reset: synchronous reset:

always@(posedge clock or posedge reset) always@(posedge clock)

begin begin
if(reset) if(reset)
output = 0; output = 0;
else else
output = 1; output = 1;
end end
Procedural Assignments:

• Blocking Assignments
• Non Blocking Assignments

Blocking Assignments:
They are executed sequentially
They blocks the simulation until the current instruction is executed
Eg: a = 1;
#10 b = 0; // b is executed after 10 time units
Non Blocking Assignments:
• These instructions executes at a time if there is no delay in between
instructions

Eg:
a <= 10;
b<= 20 // both a and b executes at same simulation time
Block Statements:
• Begin – end block
• Fork – join block

Begin – end block:

instructions in begin – end block executes sequentially
Eg:
begin
a = 1;
b = 2; after a , b executes
end
Fork – join block:
• The instructions under this block executes parallel

Eg:
fork
a = 1;
b = 2; // a and b executes at same time
join
Timing control statements:
• Delay control
• Level_Sensitive control
• Event timing controls

Delay Control:
• A delay control is introduced by symbol #

Eg: #10 a = b ; // after 10 time units b is assigned to a

Level_Sensitive control:
• Wait_statement
it is a special form of event control. Its nature is level_sensitive
Eg:
begin
wait(enable)
begin
#10 a = b;
#10 c = d;
end
Event timing control:
• It is based on any signal or clock

Eg:
begin
@(posedge clock)
end
Branching construct:
• If – else
• Case
1.Full case
2.parallel case
If else:
• The if construct checks a specific condition and decides execution
based on result

Eg:
if(condition)
x = y;
else
x = z;
Case statement:
• Multiway decision statement that tests whether that tests whether an
expression matches one of a number of othe expressions and
branches accordingly

Eg:
case(a)
0 : x = y;
1 : x = z;
default x = c;
endcase
Loops:
• for loop
• While loop
• Repeat loop
for loop:
• It executes in 3 steps
1. initialize a variable that controls number of loop executed
2. it exits the loop when number exceeds
3. it controls the loop variable

Eg:
for(I = 0;i<10;i =i + 1)
begin
$display(“Aricent”);
end
While loop:
• Executes a statement until an condition becomes false

Eg:
while(condition)
begin
//statements
end
Repeat loop:
• Executes a statement , fixed number of times

Eg:
repeat(n)
begin
$display(“Aricent”);
end
Tasks and Functions:
• Functions:
Functions have at least one input argument
Functions must not include delays
Eg:
function x;
input a;
begin
f = a;
end
//calling a function
x(7); //therefore the value of f is 7
Tasks:
• Tasks can enable other tasks and functions
• Tasks may include delay and timing control

Eg:
task abc;
begin
a = 10;
b = 20;
end
//calling a task
abc;
Compiler directives and System tasks:
• System Tasks:
• $display,$write,$strobe, $monitor
• $time , $realtime
• $stop , $finish
File input and output system tasks:
• $fopen,$fclose,$readmemb
Compiler directives:
‘include,’define,’timescale
System Tasks:
• $display or $write - it displays the specified variables once when
command is executed
Difference between $display and $write
$display automatically adds new line character whereas $write task
does not
• $strobe: - display simulation data at a selected time(at the end of
current simulation time),when all the simulation events that have
occurred for that simulation time.
• $monitor: - Each time a variable or an expression in the argument list
changes value the entire argument list is displayed at the
end of the time step
• $finish: This task makes the simulator exit and pass control back to
host operating system
• $stop : causes simulation to be suspended
• $random: provides mechanism for random numbers
• $test$plusargs(string):
This system function searches the list of plusargs for the
provided string
The plusargs present on the command line are searched in the
order provided
Compiler directives:
‘define:
creates a macro for text substitution
can be used both inside and outside of module
Syntax:
‘define dt_width 8
‘define ad_depth 256
module ram(input clk,reset,din,wadd,radd,dout);
reg[(‘dt_width-1):0]mem[(‘ad_depth-1):0];
endmodule
‘include:
• Used to include global definitions

File – state.v
‘define hold 1
‘define reset 1
‘define set 2

Program:
‘include “state.v”
module abc(------------);
reg a;
a = ‘hold; // the value of hold(which is in state.v) is assigned to reg a
-------------------------------------
‘timescale:
• Specifies the time unit and time precision of the modules that
follow ‘timescale
Eg:
‘timescale 10ns/10ps
module top();
reg clk;
------------
initial
begin
clk = 1’b0;
forever #10 clk = ~clk;
end
endmodule
‘ifdef:
• It checks that a macro has been defined and if so,compiles the code
that follows
• If the macro has not been defined the compiler compiles the code
following the else directive
• Conditional compiler directive
• Executed during compilation time
Synchronous Dual Port RAM:
rd_addr

clock
reset
read data_out
write RAM
data_in

wr_addr
 Verilog code for RAM
module dual_ram(reset,clock,read,write,rd_addr,wr_addr,data_in,data_out);

parameter RAM_WIDTH=8;
parameter RAM_DEPTH=16;
parameter ADDR_SIZE=4;
input clk,read,write;
input[RAM_WIDTH-1:0]data_in;
input[ADDR_SIZE-1:0]rd_addr,wr_addr;
outputreg[RAM_WIDTH-1:0]data_out;
reg[RAM_WIDTH-1:0]mem[RAM_DEPTH-1:0];
 always@(posedge clk)
begin
if(write)
mem[wr_addr]<=data_in;
if(read)
data_out<=mem[rd_addr];
end
endmodule
 References:
• IEEE reference manual
http://www-inst.eecs.berkeley.edu/~cs150/fa06/Labs/verilog-ieee.pdf

Textbook:
1. Verilog HDL A guide to Digital Design and Synthesis by Samir palnitkar