The Silicon Laboratories C8051F020

The Silicon Laboratories
C8051F020
Enhanced 8051
Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

Overview
• Timing – system clocks
• CPU Execution timing
• Software Delays
• Timers
• On-chip “external” RAM
• A/D and D/A Conversion
• Temperature Sensor
• Additional Timers and Interrupts
SFRs for Subsystems
• Control registers:
– XXXCN (WDTCN, ADC0CN, DAC0CN, TMR3CN)
• Configuration registers:
– XXXCF (ADC0CF, AMX0CF, EMI0CF)
• Data registers for subsystems:
– ADC0H, ADC0L, DAC0H, DAC0L
• Many others.....

System Clocks
• Internal clock
oscillator
– default at reset
– 2 MHz default
frequency
– configured by SFR
OSCICN
• External oscillator
installed on board
– 22.1184 MHz
– configured by SFR
OSCXCN

Internal Osc Configuration
OSCICN
Missing clock Internal Osc.

detector enable Internal Osc.
frequency
system clock freq. control bits
ready
select 00 – 2MHz
0 = internal 01 – 4 MHz
1 = external 10 – 8 MHz
(internal by 11 – 16 MHz
Default Sysclk default)
f = 2 MHz Internal Osc.
enable
T = 0.5 s (enabled by
default)

External Osc. Configuration
OSCXCN
External Osc. mode bits External Osc.

freq. control bits
Crystal Osc. 00x: Off. XTAL1 pin is grounded internally.
valid flag Sets frequency
010: System Clock from External CMOS Clock on
range
XTAL1 pin.
011: System Clock from External CMOS Clock on Depends on

XTAL1 pin divided by 2. mode bits
10x: RC/C Oscillator Mode with divide by 2 stage.
110: Crystal Oscillator Mode
111: Crystal Oscillator Mode with divide by 2 stage.

Development Board Oscillator

To use 22.1184 MHz external oscillator
110: Crystal Oscillator Mode 111: f > 6.7 MHz
Step 1. Enable the external oscillator.

Step 2. Wait at least 1 ms.
Step 3. Poll for XTLVLD => ‘1’.
Step 4. Switch the system clock to the external oscillator.

Instruction Timing
• C8051F020 – Pipelined architecture
• Machine cycle = clock cycle
• Most instructions take 1 or 2 clock cycles
• Total of 109 instructions
• Summary of instruction timing:

Delay Loops
djnz acc, $ ; 3 cycles if no jump,
; 4 cycles if jump
# cycles  (acc) x 4
Execution time = # cycles x (T)
With 22.1184 MHz External Osc. With 2 MHz Internal Osc.
T = 45.211 ns T = 0.5 s
Execution time = (acc) x (180.8 ns) Execution time = (acc) x (2 s)

Sample Configuration
• Use 22.1184 MHz external oscillator
Main:
mov WDTCN, #0deh ; disable watchdog timer
mov WDTCN, #0adh
mov OSCXCN, #67h ; enable external crystal
; oscillator at 22.1184MHz
clr A ; wait at least 1ms
djnz acc, $ ; wait ~510us (255 x 4 x 0.5us) = 510 us)
djnz acc, $ ; wait ~510us
osc_wait: ; poll for XTLVLD-->1

mov a, OSCXCN
jnb acc.7, osc_wait
orl OSCICN, #08h ; select external oscillator as

; system clock source

Timers
• Original 8051 has 2 Timers, T0 and T1
• Can think of timers as binary counters
• Clock is derived from system clock (frequency is
configurable)
• Timer registers can be read via mov instructions
• Events (interrupts or flag bits set) occur when
timers overflow (eg. count up from FF  00)
• Can be used to create waveforms, measure time
intervals, set frequency of events, etc.

C8051F020 Timers
• As a “timer”, timers increment on clock tick.

• As a “counter”, timers increment on edge of external signal.
• Size of timers can be configured.
• Timers can count from arbitrary initial value with the “Auto-reload”
feature.
• “Capture” allows the timer to be “frozen” when an event occurs.
• Timers 2 and 4 can be used to set baud rate for uarts.

Timer Clock Sources
CKCON: Clock Control Register
Timer0
Timer clock selects
Timer4
0 = system clock  12 (for compatibility
with original 8051,
and for slow stuff)
1 = system clock

Configuring Timers
• TCON and TMOD used to configure Timer0 and
Timer1
TCON: Timer Control Register
Timer 1 Timer 1 run control These deal with external

Overflow 0 = disable Timer 1 interrupts
Flag 1 = enable Timer 1

Configuring Timers
TMOD: Timer Mode Register
Timer 1 Timer 0
GATEn: 0 = timer enabled with TR only
1 = timer enables with TR and \INT
C/Tn: 0 = timer incremented by clock input

1 = counter incremented by edge on external Tn pin

Configuring Timers 0 and 1
Mode 0 and 1 (diagram is for Timer 0)
(mode 1
8 bits)

Configuring Timers 0 and 1
Mode 2 TH0 holds reload value
8-bit reloadable counter TL0 holds the count
When timer overflows,

it resets to reload value.

Using Timers For Periodic Events
Using Polling
• Set mode to be timer, use appropriate clock
and timer size
• In main program
– Check for overflow flag (polling)
– When overflow flag occurs
• Do event
• Reset timer overflow flag
• Reset timer initial value (unless using auto-reload or
initial value of 0 is OK)
• Continue checking

Using Timers For Periodic Events
Using Interrupts
• Set mode to be timer, use appropriate clock
and timer size
• Set timer to interrupt on overflow
• In Interrupt Service Routine
– Do event
– Reset interrupt flag
– Reset timer to initial value (unless using auto-
reload)
– Return from interrupt

Time to use timers!

Using Timers as Counter
• Set mode to be counter, with appropriate
size (8, 13 or 16 bits)
• Initialize counter to zero
• Enable counter
• Counter can be read and reset by main
program.

Using Timers to Measure Time
Using Timers:
– Configure timers with mode 0 or 1 (13 or 16-bit
timer) and desired system clock.
– In main program, wait for initial event.
– Start the timer.
– Each time the timer overflows, a register should
be incremented using an interrupt service
routine.
– When the second event occurs, disable the
interrupts and the timer in the main program.

Measuring Pulses....
And using the Config tool

Memory Interface
address
data
CPU Memory
control

On-chip “External” RAM
“external” RAM
Can add MORE
accessed with
memory
movx instruction
Interfaced using
External Data
Memory Bus
Memory Expansion
Can add more external RAM
port 4 implements
control lines
ports 5 and 6
implement
address bus
port 7 implements
data bus

Using External RAM
• Used to hold large data sets
• Accessed with movx instruction
– MOVX A, @Ri Move external data to A register
– MOVX @Ri, A Move A to external data (8-bit address)

– MOVX A, @DPTR Move external data (16-bit address) to A
– MOVX @DPTR, A Move A to external data (16-bit address)
• Remember that the data pointer can be

incremented, but not decremented.

Move some data….

Digital to Analog Conversion
0001 0010
Digital Signals: 04, 00, 06, 12, 1D, 22, 21….
Analog Signal
ideal
actual

• Two general types
– Weighted D/A Converter (4-bit example)
R
digital input Q3
register
2R analog output
4 Q2 Rout
4R
Q1
1111
Q0 8R
1100
1000
0100
0000

Ladder D/A Converter (4-bit example)
digital input 2R analog output

Q3
register
4 R 1111
2R
Q2 1100
R
2R
Q1 1000
2R R
Q0 0100
2R
0000

Digital/Analog Converters in
C8051F020
DAC0 and DAC1 (identical)
When
disabled,
output is high
impedance
Data registers
12 bit digital value
DAC0CN: DAC Control Register
DAC Data Format

000:
DAC Enable 001:
0 = disable 010:
1xx:
1 = enable
DAC Mode
00: DAC updates occur on a write to DAC0H.
01: DAC updates occur on Timer 3 overflow.

DAC Registers
DAC0H (8) DAC0L (8) DAC1H (8) DAC1L (8)
• In mode 0 (default), analog output is

updated on a write to DAC0H (or DAC1H)
• Write to DAC0L (or DAC1L) simply
latches that value, but does not cause the
conversion.
conversion
mov DAC0L, #1Fh occurs after this
mov DAC0H, #0F5h instruction
Conversion Synchronization
• Use Timer overflows to synchronize DAC when it
is important to have smooth output waveforms.
Using software loops Using timer overflows.

which may be
interrupted.

Output Voltage Swing
0 analog range Vref – 1 lsb
000h digital range FFFh

(4095)
Example: Vref = 3V
3V V Range = 0 to (3V-732.6 V)
= 732.6
4095 levels level
0 to 2.999267

Reference Voltage
• Can be an
external voltage
on pin VREFD
• Can be the
internal
reference
voltage VREF
(2.4V)

Configuring VREFD
REF0CN
BIASE: ADC/DAC Bias Generator Enable Bit.

(Must be ‘1’ if using ADC or DAC).
0: Internal Bias Generator Off.
1: Internal Bias Generator On.
REFBE: Internal Reference Buffer Enable Bit.

0: Internal Reference Buffer Off.
1: Internal Reference Buffer On.

Creating Analog Output...

Analog to Digital Conversion
V Digital value
01111110
01111100
11101110
11111110
01110000
10110000
10111110
01111110
11111110
time time
Analog A/D
Converter Digital (8-bit)
GND

DAC
Basic idea is to compare analog input to value produced

by DAC and use logic to adjust the digital output so that
it properly represents the analog input.
A/D converters classified based on what logic is used.

Counting Converter
DAC
n
Count from 0 to 2n, when DAC output is higher than Input,

then flag changes.
Kind of slow – takes up to 2n clock cycles to convert.

Successive Approximation
DAC
Starting at MSB, set

each bit to 1, and if it
Example... first 3 bits trips the comparator,
110000000000
reset to 0. If not, hold
analog
101000000000 at 1. Repeat for all
100000000000 bits.
100000000000
110000000000
101000000000
.....
Precision
Analog A/D n Digital
Converter Analog Digital
0.00 0000
0.25 0001
0.50 0010
Examples: 0.75 0011
1.00 0100
Analog Range: 0V-4V 1.25 0101
Digital: n=4 1.50 0110
1.75 0111
2.00 1000
4 Volts .25 V/bit 2.25 1001
Precision: 2.50 1010
16 values 2.75 1011
3.00 1100
3.25 1101
3.50 1110
3.75 1111
4.00
C8051F020 A/D Converters
• ADC0
– 12-bit Successive Approximation (SAR)
– 100ksps (kilo-samples per second)
• ADC1
– 8-bit SAR
– 500ksps

ADC0
Analog source options SFRs
Reference voltage options

Conversion sync options

AMX0CF – AMUX0 Configuration Register
Differential pair inputs:
+
V
-
V can be positive or negative
0 – single-ended analog inputs

1 – differential pairs
AMX0CF

AMX0SL – AMUX0 Channel Select Register
Example:
AMX0CF = 0000 (all single
ended analog inputs) then:
AMUX0
0000 – AIN0
0001 – AIN1
0010 – AIN2
0011 – AIN3
0100 – AIN4
0101 – AIN5
0110 – AIN6
0111 – AIN7
1xxx – Temp Sensor
AMUX0 address bits

Depend on AMX0CF
AMX0SL

ADC0CF – ADC0 Configuration Register
Bit7-Bit3:
SAR Conversion Clock
Period Bits
Bit2-Bit0:
Internal Amplifier Gain
000: Gain = 1
001: Gain = 2
010: Gain = 4
011: Gain = 8
10x: Gain = 16
11x: Gain = 0.5
ADC0CF

ADC0CN – ADC0 Control Register
AD0EN 0 = disabled
1 = enabled
AD0TM Track mode bit
AD0INT 0 = conversion not

completed since flag was
cleared (must be cleared by
software) 1 = conversion has
been completed
AD0BUSY 0 = conversion not

in progress 1 = conversion in
progress
ADC0CN

ADC0CN – ADC0 Control Register
ADC0CN
Bit3-2: ADC0 Start of Conversion Mode Select.
If AD0TM = 0 (tracking mode on:
00: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY.
01: ADC0 conversion initiated on overflow of Timer 3.
10: ADC0 conversion initiated on rising edge of external CNVSTR.
11: ADC0 conversion initiated on overflow of Timer 2.
If AD0TM = 1: Same as above except conversion takes 3 SAR clock cycles longer
Bit1: ADC0 Window Compare Interrupt Flag.

This bit must be cleared by software.
0: ADC0 Window Comparison Data match has not occurred since this flag was last
cleared.
1: ADC0 Window Comparison Data match has occurred.
Bit0: ADC0 Left Justify Select.

0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
Selecting VREF, Gain
• Maximum VREF = 3.3V (Vdd)
• Suppose analog range is about 0-3V
– No Gain needed
– External VREF of 3V
0r
– Gain = .5 (so analog range becomes 0-1.5V)
– VREF from DAC0 of 1.5V
• Suppose analog range is low: 0-0.01V

– Use max gain of 16 (so range is 0-0.16V)
– VREF from DAC0 or external, 0.16V)

ADC0 Example 1
+
Vin -
2.0V
• Differential input (can be negative or positive) on

AIN0 and AIN1 (channel select AIN0)
• Convert on timer 2 overflow
•Amplify by 4
•Right justified data
•Interrupt each conversion
•External Vref = 2.0V

ADC0 Example 1
Data Conversion:
Gain = 4
VREF = 2.0V
Note: Vin limited to range of -.5V to +.5V
Gain
Vin ADC0H: ADC0L Code  Vin   2n
+.5V 07FFh 00000111:11111111 VREF
+.25V 0400h 00000100:00000000 n = 12 for single-ended
0 0000h 00000000:00000000
inputs, n = 11 for differential
-.25V FC00h 11111100:00000000 Values are sign-extended.

-.5V F800h 11111000:00000000

ADC0 Example 2
Vin1
Vin2
Vin3
• Single ended inputs (3 of them)

• Convert on timer 2 overflow Channel can be
• Amplify by 2
modified in the
• Right justified data
• Interrupt on conversion
program
mov AMX0CF, #060h ; AMUX Configuration Register

mov AMX0SL, #000h ; AMUX Channel Select Register
mov ADC0CF, #009h ; ADC0 Configuration Register
mov ADC0CN, #08Ch ; ADC Control Register

Conversion Calculations
0 analog range Vref – 1 lsb
000h digital range FFFh

(4095)
There are 4096 different digital values corresponding to 0-Vref.
Find the voltage per least significant bit: Vref
4096
Now find analog value corresponding to some digital value Xd
Vref
Va = x Xd
4096

Become ADC Converts....

ADC0 Programmable Window Detector
• Set limits for Analog input value

• Analog value continuously compared to the
limits
• System is notified if analog input is out of
bounds.

Window Limit Registers
AD0WInt = 1
ADC0LTH: ADC0LTL ADC0GTH: ADC0GTL
AD0WInt = 1
ADC0GTH: ADC0GTL ADC0LTH: ADC0LTL
AD0WInt = 1

Programmable Window Detector
EXAMPLE

ADC0CN
Bit1: ADC0 Window Compare Interrupt Flag.

This bit must be cleared by software.
0: ADC0 Window Comparison Data match has not occurred since this flag
was last cleared.
1: ADC0 Window Comparison Data match has occurred.

Example – Detect Darkness
• Using light sensor setup, with “dark”
corresponding to .25 * VREF
• When “dark” is detected, use an interrupt service
routine to turn on the LED.
• When it becomes light enough, (.5 VREF) turn AD0WInt = 1
LED off
Gain
Code  Vin   2n
VREF
1 ADC0GTH: ADC0GTL
Code  (0.25  VREF )   212 = 400h ADC0LTH: ADC0lTL
VREF
1
Code  (0.5  VREF )   212 = 800h
VREF AD0WInt = 1
mov ADC0LTH, #004h; ADC Less-Than High Byte Register
mov ADC0LTL, #000h; ADC Less-Than Low Byte Register
mov ADC0GTH, #008h; ADC Greater-Than High Byte Register
mov ADC0GTL, #000h; ADC Greater-Than Low Byte Register
mov EIE1, #004h ;Extended Interrupt Enable 1

cseg at 043h ; set the interrupt vector
ljmp adw_int
….
adw_int: clr AD0WINT ; Clear interrupt flag (ADC0CN is bit addressable)
mov a, ADC0H ; check MSB of ADC to see which condition it is
clr C
subb a, #04 ; Is it less than 04?
jnc off_light ; if not, must be time to turn light off
setb LED ; if so, turn on light and return
sjmp over
off_light: clr LED
over: reti

Temperature Sensor
• Selected with the AMX0SL register

• Otherwise treated the same as other ADC inputs
• Using above equation, and ADC0 settings and conversion equation, we can convert
temperature to digital value.

Temperature Sensor Example
Letting the assembler do more for us.

How hot is it?

ADC1 – the “other” ADC
8-bit ADC, 500 ksps
Control registers
similar to
ADC0, but
simpler

ADC1
AIN1.0 – AIN1.7 shared with P1.0 – P1.7

Must set P1MDIN for ANALOG inputs, and
it is NOT necessary to turn on crossbar switch

Why not Crossbar?
Bypass
crossbar

The “Other” Timers
• Timer 3 – auto-reload feature, more clock sources

• Timers 2 and 4 – almost identical to each other
– auto-reload feature
– capture feature
– baud rate generator for UARTS (serial interface)

Timer 3
• Clock sources:
– External oscillator  8 (allows for real-time clock input for timed applications)
– Sysclk or Sysclk  12 (like all other timers)
• Always 16-bit, auto-reload.
– Write “reload” value to TMR3RLH : TMR3RLL
– Defines the time between overflows
• Can be used to start ADC conversion
• Can be used for SMBbus timing

Auto-reload Example
Suppose we want to sample the ADC every 1ms.
• How many counts for 1ms with:
– Internal oscillator (2 MHz)?

2 MHz * 1ms = 2000 counts (7D0h)
0000
FFFF
07D0h counts
…
F830 Auto-reload value = 0000 - 07D0 = F830h
…
= - 07D0h
0000

TMR3RL – Reload Register
mov TMR3RLH, #(F8h) ; init reload values
mov TMR3RLL, #(30h)
or
SYSCLK EQU 2000 ; SYSCLK frequency in kHz

TC_1ms EQU (SYSCLK)*1 ; number of timer counts in
1ms
Assembler can do these calculations
mov TMR3RLH, #HIGH(-TC_1ms); init reload values

mov TMR3RLL, #LOW(-TC_1ms)

Timers 2 and 4 - Similar
Capture: Can latch the timer value into a separate

latch when certain events occur

Timer 2 – Capture Mode
Interrupt on
Capture occurs on
overflow or on
edge of T2EX when Capture register capture when
EXEN2 enables it.
enabled
Capture Mode to Measure Intervals
1 2
8051
TEX2
time interval
RCAP2  Timer2 value, RCAP2  Timer2 value,
EXF2 flag goes high, EXF2 flag goes high,
Timer2 interrupt generated if Timer2 interrupt generated if
enabled enabled
If time interval is less than FFFF counts, then ISR can just
subtract captured value 2 from captured value 1 to find time
interval. Otherwise ISR must also keep track of overflows.
Programmable Counter Array
• The ultimate timer/counter!
– SIX different possible clock sources
– SIX modes of operation
• Capture modes (with 3 edge options)
• Software timer (Compare) mode (interrupt when timer register
= compare register)
• High speed output : (output pin is toggled when timer register
= compare register)
• Frequency output: (square wave produced at a specified
frequency)
• 8-bit Pulse-Width-Modulation mode
• 16-bit Pulse-Width-Modulation mode

PCA Block Diagram
Clock sources from
timer overflow as well
as external clock on ECI
or sysclk derivatives
Output pins for PWM

and other waveforms

PCA Capture/Compare Modules
• 5 modules: each module can operate in one of the 6 modes
• Specified by SFR PCA0CPMn

PCA Interrupts
• PCA only has one interrupt vector, but can
be triggered by many things.

PCA Capture Mode
• Transition (positive, negative, or either) on CEX
pin causes current timer value to be captured.
• CCF flag indicates capture has occurred (and
causes interrupt if enabled.

PCA Compare Mode (software timer)
• Set compare registers with software

• CCF or interrupt when compare reg = timer

PCA High Frequency Output
• Similar to compare mode, but CEX is toggled on
each compare match.

Frequency Output Mode
• Programmable frequency square wave on
CEXn
• High byte of PCA0CPn holds counts
between toggles
• Frequency defined as follows:
FPCA
FCEXn 
2 PCA0CPHn

8 bit PWM mode
• Pulse Width Modulation
Tp
T
“Average” value of signal is
Duty Cycle = Tp proportional to duty cycle.
T
Pulse width modulation means varying the duty cycle.
Used to provide “pseudo” analog signal.

8 bit PWM Mode
• T is set by the clock source of the PCA
• Duty cycle is set by high byte of PCA0CPn
(256  PCA0CPHn)
DutyCycle 
256

16 Bit PWM Mode
• Same as 8-bit but entire PCA0CPn register
is used to set duty cycle.
(65536  PCA0CPn)
DutyCycle 
65536

Seven Segment Display!
Lab report due next Wednesday

The Silicon Laboratories C8051F020

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Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

Missing clock Internal Osc.

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

External Osc. mode bits External Osc.

011: System Clock from External CMOS Clock on Depends on

110: Crystal Oscillator Mode

111: Crystal Oscillator Mode with divide by 2 stage.

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

110: Crystal Oscillator Mode 111: f > 6.7 MHz

Step 1. Enable the external oscillator.

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

• Summary of instruction timing:

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

osc_wait: ; poll for XTLVLD-->1

orl OSCICN, #08h ; select external oscillator as

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

• As a “timer”, timers increment on clock tick.

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

CKCON: Clock Control Register

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

Timer 1 Timer 1 run control These deal with external

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

C/Tn: 0 = timer incremented by clock input

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

When timer overflows,

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

And using the Config tool

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

– MOVX @Ri, A Move A to external data (8-bit address)

– MOVX @DPTR, A Move A to external data (16-bit address)

• Remember that the data pointer can be

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

Digital Signals: 04, 00, 06, 12, 1D, 22, 21….

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

digital input 2R analog output

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

DAC Data Format

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

• In mode 0 (default), analog output is

Using software loops Using timer overflows.

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

000h digital range FFFh

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems

BIASE: ADC/DAC Bias Generator Enable Bit.

REFBE: Internal Reference Buffer Enable Bit.

Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems