Instruction Set-1

By: Aqib Asad

National College of Business Administration and Economics
(Dept. of Computer Science & IT)
Contents

 Instruction set Architecture

 Types of instructions
 Instruction format
 Address formats
 Different types of ISA’s
 Major choices
 Memory addressing
 Addressing modes
Instruction Set

 The complete collection of instructions that are understood by a CPU

 Machine Code
 Binary
 Usually represented by assembly codes

 ISA specifies the set of opcodes (machine language), and native commands
implemented by a particular processor.
 Instruction set

 An instruction set, or instruction set architecture (ISA), is the part of the

computer architecture related to programming, including the
 Native data types
 Instructions
 Registers
 addressing modes
 memory architecture
 interrupt and exception handling
 and external I/O.
Types of Instructions

 All computers provide a full set of following operational instructions for:

 Arithmetic and Logic

(integer Add, Sub, multiply, division, and, or)
 Data Transfer
(Load Store, Move instructions with memory addressing)
 Control
(Branch, Jump, procedure call and return)
 The following support instructions may be provided in computer with different levels
 System
(operating system call, Virtual Memory Management)
 Floating Point
(Add, multiply, divide and compare)
 Decimal
(BCD add, multiply and Decimal to Character Conversion)
 String
(String move, compare and search)
 Graphics
(Pixel and vertex operations, compression / de-compression operations)
Instruction format

 An instruction format defines the layout of the bits of an instruction, in terms

of its constituents parts.
 An instruction format must include an opcode and, implicitly or explicitly,
zero or more operands.
 Each explicit operand is referenced using one of the addressing mode that
is available for that machine.
 The format must, implicitly or explicitly, indicate the addressing mode of
each operand.
 Simple Instruction Format

 The instruction is divided into fields, corresponding to the basic elements of

the instruction.

 Instruction is read into an Instruction Register (IR)

 The CPU must be able to extract the data from the various instruction fields
to perform the required operation.
 Operation code (Op code)  Do this…

 Specifies the operation to be performed (e.g.. ADD, SUB, I/O).

 Opcode field which stands for operation code and it specifies the particular operation that is to be performed.

 Source Operand reference  To this…

 The operation may involve one or more source operands, that is, operands that are inputs for the operation.

 Operands fields which specify where to get the source and destination operands for the operation specified by the opcode.

 Result Operand reference  Put the answer here…

 The operation may produce a result.

 Next Instruction Reference  When done that, do this...

 It tells the CPU where to fetch the next instruction after the execution of this instruction is complete.
Different Instruction Formats

a. Zero Address Instruction

b. One Address Instruction
c. Two Address Instruction
d. Three Address Instruction
Instructions Addressing

 Zero Address Instruction

 One Address Instruction
 Two Address Instruction
 Three Address Instruction
 Zero Address Instruction

Expression: X = (A+B)*(C+D)
 One Address Instruction

Expression: X = (A+B)*(C+D)
 Two Address Instruction

Expression: X = (A+B)*(C+D)
 Three Address Instruction

Expression: X = (A+B)*(C+D)
16 Different types of ISAs

 Determined by means for storing data in CPU:

 The major choices are:

A stack
An accumulator
A set of registers
17 ISA Architectures

 Stack architecture:
 Operands are implicitly on top of the stack

 Accumulator architecture:
 One operand is in accumulator (register) and the others are in
memory
 (Essentially this is a 1 register machine)
 (Found in earlier machines…)

 General purpose registers:

 Operands are in registers or specific memory locations
 Stack Architecture
18

 Simple expression
evaluation
 Short instruction yields good
code density ALU

 Stack can not be randomly

accessed
 Inefficient stack is a Stack

bottleneck

MBR
19 Stack Architecture

 A=B+C
 A, B & C are memory addresses
 push B
push C
add
pop A
 Accumulator Architecture
20

 Early machines based on

single register
 Supports single/zero address Accum.

instructions
 Arithmetic instructions
require memory access
 Short instruction ALU

 Memory traffic high

MBR
21 Accumulator/Single Register
Architecture
 A=B+C
 A, B & C are memory addresses
 load B
add C
store A
 load regA, memoryX not allowed
 Complex operations too slow

September 6, 2017
 General-Purpose Architecture
22

 Most general model for code

generation
 All operands must be named, Registers

leading to longer code

 Register-register
 Register-memory ALU

MBR
23 General-Purpose Architecture

 A=B+C
 A, B & C are memory addresses
 load R 1, B load R1, B
load R 2, C add R1, C
add R 1, R 2 store A, R1
store A , R1
Memory Choices

 Stack Architecture:
 Accumulator Architecture
 General Purpose Register Architecture
 Register – memory
 Register – Register (load/store)
 Memory – Memory Architecture (Obsolete)
 Taxonomy of Instruction Set ….. Cont’d
25

Basic Differentiator: The type of

internal storage of the operand
Major Choices of ISA:
 Stack Architecture:
 Accumulator Architecture
 General Purpose Register Architecture
 Register – memory
 Register – Register (load/store)
 Memory – Memory Architecture (Obsolete)
26
Stack Architecture
Processor

 Both the operands are TOS

implicitly on the TOS
 Thus, it is also referred to as
Zero-Address machine
 The operand may be either
an input (orange shade) or ALU
result from the ALU (yellow
shade)
 All operands are implicit
 The first operand is removed ....
from the stack and the Memory
second operand is
replaced by the result
....
 Stack Architecture
27
To execute: C=A+B
ADD instruction has TOS
implicit operands for the
stack – operands are
written in the stack using
PUSH instruction

PUSH A
PUSH B ALU

ADD
POP C
 Accumulator Architecture
28  An accumulator is a special register Processor
within the CPU that serves both as
the implicit source of one operand
and as the result destination for
arithmetic and logic operations.

 Thus, it accumulates or collect data

and doesn’t serve as an address
register at any time
 Limited number of accumulators – ALU
usually one is used

 The second operand is in the

memory, thus accumulator based
machines are also called 1-address
....
machines Memory

 They are useful when memory is

expensive or when a limited
number of addressing modes are ....
used
 Accumulator Architecture
29
To execute: C=A+B
ADD instruction has implicit
operand A for the
accumulator, written using
LOAD instruction; and the
second operand B is in memory ALU
at address B

Load A
ADD B
Store C
.
.
 General Purpose Register Architecture
30
 Many general purpose registers are available within CPU
 Generally, CPU registers do not have dedicated functions and can
be used for a variety of purposes – address, data and control
 A relatively small number of bits in the instruction is needed to
identify the register
 In addition to the GPRs, there are many dedicated or special-
purpose registers as well, but many of them are not “visible” to the
programmer
 GPR architecture has explicit operands either in register or memory
thus there may exist:
- Register – memory architecture
- Register – Register (Load/Store) Architecture
- Memory – Memory Architecture
General Purpose Register Architecture
Register – Memory Architecture
 One explicit operand is in a register
and one in memory and the result ....
goes into the register R3
 The operand in memory is R2
accessed directly R1
To execute: C=A+B
Processor ....
ADD instruction has explicit
operand A loaded in a register and
the operand B is in memory and ALU
the result is in register

Load R1, A
ADD R3, R1, B ....
Memory
Store R3, C

....
31
 General Purpose Register Architecture
32  The explicit operands in memory are Register – Register (Load/store)
first loaded into registers temporarily Architecture
and
....
 Are transferred to memory by Store R3
instruction R2
To execute: C=A+B R1
ADD instruction has implicit operands A
Processor ....
and B loaded in registers

Load R1, A
ALU
Load R2, B
ADD R3, R1, R2
Store R3, C
....
 Both the explicit operands are not Memory
accessed from memory directly, i.e.,
Memory – Memory Architecture is
obsolete

....
33 Comparison of three GPR Architectures

Register-Register
Advantages
 Simple, fixed-length instruction decoding
 Simple code generation
 Similar number of clock cycles / instruction

Disadvantages
 Higher Instruction count than memory reference
 Lower instruction density leads to larger programs
34 Comparison of three GPR Architectures

Register- Memory
Advantages
 Data can be accessed without separate Load first
 Instruction format is easy to encode
Disadvantages
 Encoding a register number and memory address in each instruction may
restrict the number of registers
 CPI vary by operand location
35 Comparison of three GPR Architectures
 Memory- Memory
Advantages
 Most compact
 Doesn’t waste registers for temporary storages
Disadvantages
 Large variation in instruction size
 Large variation in work per instruction
 Memory bottleneck by memory access
 Pros and cons for each ISA type
Machine Advantages Disadvantages
Type
Stack Short instructions Lack of random access
Good code density Efficient code hard to get

Simple to decode Stack is often a bottleneck

instruction
Accumula Minimal internal state Very high memory traffic
tor Short instruction

Simple to decode
instruction
Register Lots of code generation Longerinstructions
option Complex instructions
Efficient code (compiler
options)
36