IEEE PAPER

PRESENTATION

GUDE ADITYA
611627
 Power Efficient
Priority Encoder
1.ABSTRACT
2.FOUR PHASE POWER CLOCK
3. EXISTING TECHNIQUES
4. EXPRESSIONS FOR PRIORITY ENCODER
5.BASIS OF THE PROPOSED LOGIC
6.PROPOSED CIRCUITS
7.POWER CONSUMPTION ANALYSIS AND
COMPARISON
8. CONCLUSION
9. REFERENCES
 ABSTRACT

 It contains a CMOS-based new design approach for

a low power 4:2 Priority Encoder
 The proposed designs are compared with the
standard logic styles– PFAL, ECRL and 2n2n2p
 The simulation is carried out in NI-Multisim
software at 0.5 µm CMOS technology
 Four-phase power clock
 Power-clock cycle consisting of four intervals:-
 Evaluate (E)- The outputs corresponding to the input signals are
evaluated.
 Hold (H)-The outputs are maintained at the present state
 Recover (R) - Energy is recovered and transferred to the power
supply
 Wait (W)-It is used for next cycle to start
 EXISTING TECHNIQUES

A. ECRL(EFFICIENT CHARGE RECOVERY LOGIC CIRCUIT)

B. 2n2n2p
C. PFAL(POSITIVE FEEDBACK ADIABATIC LOGIC)
ECRL(EFFICIENT CHARGE RECOVERY LOGIC CIRCUIT)

 It consists of PMOS loads and NMOS

pull-down transistors.
 It uses a cross-coupled PMOS pair
2n2n2p

 Ithas cross-coupled
NMOS in addition to
the cross-coupled
PMOS.
 Itis a derived form
of ECRL
PFAL(POSITIVE FEEDBACK ADIABATIC LOGIC)

 Itis formed by two

cross-coupled
inverters to store
the output.
BLOCK DIAGRAM OF PRIORITY ENCODER
 EXPRESSIONS FOR PRIORITY ENCODER

 A priority encoder is a special type of encoder in that upon giving 2 or more

inputs at the same time, the input having the highest priority takes
precedence.

INPUTS OUTPUTS
X3 X2 X1 X0 Y1 Y0
1 X X X 1 1
0 1 X X 1 0
0 0 1 X 0 1
0 0 0 1 0 0
0 0 0 0 0 0

 Y1=X2+X3
 Y0=X3+X2’X1
 BASIS OF THE PROPOSED LOGIC

 It represents the conventional CMOS-based inverter, with the

two additional transistors
 It involves inclusion of one PMOS above and one NMOS below
 These two extra transistors form the basis of the proposed logic
which results in power minimization.
 The two MOS transistors are added in such a way that the
PMOS and NMOS are connected to pull-up and pull-down
sides
 During evaluation phase, the power supply PCLK swings up
and is tracked by the output
 In the recovery phase PCLK swings down and the voltage
stored at the output capacitor is sent back to the supply PCLK
PCLK

X Y
PROPOSED
CIRCUITS
 The simulation of the proposed logic for the
priority encoder against the standard logic
styles- 2n2n2P, PFAL,ECRL, have been done in NI- POWER
Multisim
CONSUMPTION
load capacitance-10fF
frequency range 200-800 MHz.
ANALYSIS
0.5 µm technology AND
W = 1.25µm COMPARISON
L = 0.5µm
VPCLK = 3.3V,
V= 3V (the input pulse voltage).
 The power plot featuring the power dissipation curves
PERFORMANCE ANALYSIS OF VARIOUS
LOGIC STYLES FOR PRIORITY ENCODER
Logic
Parameter 2n2n2p ECRL PFAL Proposed

Transistor count 18 14
18 14
Area per chip (µm2) 11.25 8.75 11.25 8.75
Total power dissipation (µW)
[at 400 MHz] 22.884 18.241 10.196 6.032
Total power dissipation (µW)
[at 800 MHz]
45.767 36.481 20.393 12.064
 CONCLUSION

 The proposed logic for the priority encoder are

aimed at minimizing their power dissipation.
 The simulated output waveforms verify the
working of the proposed logic and the power
consumption analysis
 This indicates that they consume the least power
compared to the standard logic
 REFERENCES
 [1] George Tom Varghese and K. K. Mahapatra, “A High Speed Low Power Encoder for
a 5 Bit Flash ADC”, IEEE International Conference on Green Technologies (ICGT), pp.
041-045, December 2012.
 [2] J. Mohanraj, P. Balasubramaniam and K. Prasad, “Power, Delay and Area
Optimized 8-Bit CMOS Priority Encoder for Embedded Applications”, International
Conference on Embedded Systems & Applications (ESA), pp. 83-85, July 2012 .
 [3] Jinn-Shyan Wang and Chung-Hsun Huang , “High-Speed and LowPower CMOS
Priority Encoders”, IEEE JOURNAL OF SOLIDSTATE CIRCUITS, Vol. 35, Issue: 10, pp.
1511-1514, October 2000.
 [4] Namrata Gupta, “ Power Aware & High Speed Booth Multiplier based on
Adiabatic Logic”, International Journal of Innovations in Engineering and Technology
(IJIET), Vol. 2 Issue 3, pp. 297-303, June 2013.
THANK YOU….