watchdog

• Microcontroller have two embedded watchdog peripherals , called

independent watchdog and window watchdog.
• It use to detect and resolve malfunctions due to software failure, and
to trigger system reset or an interrupt (window watchdog only) when
the counter reaches a given timeout value.
 Independent watchdog (IWDG)
• Useful when require the watchdog to run as a totally independent
process outside the main application
• IWDG include a 12 bit free running downcounter.
• clocked by its own dedicated low-speed clock (LSI) and stays active
even if the main clock fails.
• It will reset when the downcounter value of 0x000 is reached.
• have to constantly reset it’s counter value or it will reset MCU.
• Hardware watchdog feature is enabled through the device option bits,
the watchdog is automatically enabled at power-on if enabled.
• To avoid any reset, the key register must be reset to 0xAAAA by
software at regular interval before counter reach to 0.
 • writing the value 0xCCCC in the Key register, the counter starts counting down
from the reset value of 0xFFF
• When it reaches the end of count value (0x000) a reset signal is generated (IWDG
reset).
• Whenever the key value 0xAAAA is written in the IWDG_KR register, the
IWDG_RLR value is reloaded in the counter and the watchdog reset is prevented
• write 0x5555 in the IWDG_KR register to modify IWDG_PR and IWDG_RLR
registers . A write access to this register with a different value will break the
sequence and register access will be protected again. This implies that it is the case
of the reload operation (writing 0xAAAA).
Independent watchdog (IWDG)
• When the microcontroller enters debug mode, the IWDG counter either
continues to work normally or stops, depending on DBG_IWDG_STOP
configuration bit in DBG module.
• the prescaler divider value is valid only when the reload value update (PVU) bit
in the IWDG_SR register is reset, due to write operation to this register is ongoing
which may not valid.
• the reload register value read from this register is valid only when the prescaler
value update (RVU) bit in the IWDG_SR register is reset.
• PVU and RVU bit is set(1) by hardware to indicate that an update of the reload
value is ongoing and it is reset by hardware when PVU and RVU update operation
is completed.
• If several reload values or prescaler values are used, should wait PVU and RVU
reset before change to new prescaler and reload value.
 Min/max IWDG timeout period at 32 kHz (LSI)

Prescaler divider PR[2:0] bits Min timeout (ms) Max timeout (ms)
RL[11:0]= 0x000 RL[11:0]= 0xFFF
4 000 0.125 512
8 001 0.25 1024
16 010 0.5 2048
32 011 1 4096
64 100 2 8192
128 101 4 16384
256 110 8 32768
256 111 8 32768
Window watchdog (WWDG) features
• prescaled from the APB1 clock
• has a configurable time-window that can be programmed to detect abnormally late or early
application behavior.
• Used to detect software fault which cause program to abandon its normal sequence.
• generates an MCU reset during downcounter value is below 0x40, unless the program refresh
the downcounter value before the downcounter value go below 0x40.
• Also generate MCU reset when downcounter value is refreshed by software before the
downcounter has reached the window register value.
• It is a programmable free running downcounter. (activate through software)
• Include an interrupt called Early wakeup interrupt (EWI), triggered when the downcounter is
equal to 0x40. (can be disabled)
• WWDG enabled by setting the WDGA(activation bit) in the WWDG_CR register, then it cannot be
disabled again except by a reset.
 WWDG use free running downcounter, counting down even if the
watchdog is disabled. When the watchdog is enabled, the T6 bit (avoid
value that below 0x40) must be set to prevent generating an immediate
reset.
• T[5:0] bits contain the number of increments which represents the time delay before the watchdog
produces a reset.
• Configuration register (WWDG_CFR) contains the high limit of the window (window register value).
• To avoid reset, the downcounter must reload when downcounter have the value between 0x3F and window
register value.
• Program still can perform software reset by setting WDGA=1 and T6=0.
Advanced watchdog interrupt feature
• Early Wakeup Interrupt (EWI) can be used if specific safety operation
need to performed before the actual reset is generated.
• It is enabled by setting the EWI bit in the WWDG_CFR register.
• When the downcounter reaches the value 0x40, an EWI interrupt is
generated (interrupt service routine) can be used to trigger specific
actions before resetting the device.
• Interrupt service routine (ISR) and (EWI) can actually reload the
WWDG counter T[6:0] to avoid the WWDG reset, then trigger some
required actions.
• The EWI interrupt is cleared by writing '0' to the (EWIF) bit in the
WWDG_SR register. This bit is set by hardware when the counter has
reached the value 0x40.