FPGA Based System

Design
CEN-441
Instructor
• Asim Altaf Shah
– Bachelor Electrical Engineering (Electronics) from Bahria University, Islamabad
– Masters Electrical Engineering (Telecom & Signal Processing) CASE University,
Islamabad

• Contact info
– Office: XC Ground Floor . Room no 7
– Email: asim.altaf@bui.edu.pk

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Time Table
8:30 9:30 10:30 11:30 12:30 1:30 2:30 3:30 4:30
Days – – - – – - – – –
9:25 10:25 11:25 12:25 1:25 2:25 3:25 4:25 5:25

FPGA FPGA
Counseling hour
Monday BEE 7D BEE 7D
XC-28 XC-28

FPGA
Tuesday BEE 7D Counseling hour
XC-7

FPGA FPGA
Wednesday BEE 7A Counseling hour Counseling hour BEE 7C Meeting Hour
XC-8 XC-20

FPGA FPGA FPGA FPGA

Thursday BEE 7C BEE 7C Counseling hour Counseling hour BEE 7A BEE 7A
XC-28 XC-28 XC-14 XC-14

Friday FYP FYP FYP

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Course Objective
– The objective of this course is to teach how to design and develop complex digital
systems onto the reconfigurable devices such as Field Programmable Gate Arrays
(FPGA).
– You will be introduced to FPGA architectures (LUT, BRAMS, Interconnection Network,
DSP blocks), their design flow cycle. At the end of the course students should be able to
develop optimal digital systems requiring minimum resources using HDL.

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Course Outline
• Introduction to need of FPGA and FPGA based System Design Flow.
• Introduction to Verilog HDL.
• Gate level and structural modeling in Verilog
• Behavioral Modeling of Combinational and sequential Circuit.
• Verilog Modeling of FSM and FSMD.
• Reconfigurable Structure of Reconfigurable Devices (CPLD and FPGA).
• FPGA Design Flow including Synthesis, mapping, Place & Routing and
configuration file generation.
• Large Scale System and FPGA based System on Chip

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Books
Text Book
1. FPGA Prototyping by Verilog Examples by Pong. P . Cho. ISBN-13: 978-
0470185322
2. FPGA Based System Design by Wayne Wolf. ISBN-13: 978-0137033485
Reference book
1. Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis,”
Second Edition, 2003, Prentice Hall, TISBN: T 0130449113.
2. Michael D. Ciletti, “Advanced Digital Design with the Verilog HDL,” First
Edition, 2003, Prentice Hall, ISBN: 0130891614

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Class Learning Outcomes (CLO’s)
• The students should be able to utilize the Verilog Hardware
Description Language (HDL) to build digital circuits such as simple
CLO1:(C3) combinational, regular sequential, Finite State Machine (FSM) and FSM
with Data Path along with creating the test benches

• The students should be able to describe SRAM and Antifuse based

FPGAs along with their internal resources and is able to explain the
CLO2: (C2) FPGA resource utilization while implementing a digital circuit on
SRAM based FPGA.

• The students should be able to use the design, verification and

CLO3: (C3) implementation process and to build digital circuits on FPGA.

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Mapping of CLO to PLOs
Contribution: Average: 1, Moderate: 2, Strong: 3
CLOS Mapped PLOS Level Contibution
CLO1: The students should be able to utilize the PLO 3: Design C3 3
Verilog Hardware Description Language (HDL) to
build digital circuits such as simple combinational,
regular sequential, Finite State Machine (FSM) and
FSM with Data Path along with creating the test
benches

CLO2: The students should be able to describe PLO 1: C2 2

SRAM and Antifuse based FPGAs along with their Engineering
internal resources and is able to explain the FPGA Knowledge
resource utilization while implementing a digital
circuit on SRAM based FPGA.
CLO3:The students should be able to use the PLO 3: Design C3 3
design, verification and implementation process
and to build digital circuits on FPGA.
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Grading Rubrics
Assessment Method CLO 1 CLO 2 CLO 3
Final Exam 10 25 15
Mid Exam 16 4
Assignments 10 5 5
Quizzes 5 5
Total (100) 39 35 31

Passing marks in CLO 1 , CLO 2 and CLO 3 is 50% and above