ANALYTICAL MODELING OF

DOUBLE GATE MOSFET

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Presented by :
SHRUTI SAMANTA (24000310022)
RATUL GHOSH (24000310029)
SOUMYABRATA DE (24000310030)
TANUSHREE KOLEY (24000310048)

Under the guidance of

Asst. Prof. Aloke Kumar Das

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Down scaling

 Short channel effects (SCEs)

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Short channel effects

 DIBL
 Threshold voltage roll off
 Impact ionization
 Mobility degradation

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DIBL(Drain induced barrier lowering)

 If small channel length MOSFETs are not

scaled properly, and the source/drain
junctions are too deep or the channel
doping is too low, there can be unintended
electrostatic interactions between the
source and drain known as DIBL.

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Technique used to suppress SCEs

• Gate engineering
• Doping technique
• Channel engineering
• Drain source engineering

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Gate engineering technique

Double gate → Hetero

material used in gate
→Double material
double gate structure
→Triple material
double gate structure

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Software tools used

 MATLAB [Version 7.9.0.592(R2009b)]

 TCAD [Silvaco Deckbuild(Version 3.18.1.R)]

 Origin Pro 8 SR4 [v8.0951(B951)]

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TM-DG structure

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Value for the model parameter

 L= Gate length=60 nm
 D= Silicon thickness=25 nm
 tox= oxide thickness=2 nm
 Na=Acceptor Impurity Concentration =1014 /cm3
 Nd = Donor Impurity Concentration =1020 /cm3

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d2 Ψs Ψs qNₐ (Vgb − Vfb )
Model for − = −
double gate dx² λ² Ԑѕi λ²
structure

Substrate used as a Gaussian box

Surface potential equation

 D = Silicon thickness
 Na = Channel doping density
 Ψs = Surface Potential
 Vgb = Gate to bulk voltage
 Vfb = Flat band voltage
 β = The gate and the source/drain forms a capacitor
between two plates at an angle
 Єox = Permittivity of silicon
 Єsi =Permittivity of Sio2

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Surface potential profile with the channel
length for different gate voltages

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 From model From TCAD

Surface potential along channel

length for different structure
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Graph of surface potential profile
for different drain voltage

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 From model From TCAD

Electric field along the channel for

different structure
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Graph of electric field profile for
different drain voltage

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 From model From TCAD

Comparison on the basis of current

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 CONCLUSION

From the result and discussions section, we

can say that the TM-DG MOSFET structure
is very promising candidate to suppress
short channel effects.

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 FUTURE WORK
 Proper model approach which include the
fringing field effect
 Analysis the quantum effect
 Proper model approach for frequency
analysis
 TM-DG structure used as a solid state
device circuit
 Harmonic distortion analysis

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 REFERENCE
 International Technology Roadmap for Semiconductors,
2007.[Online]. Available: http://public.itrs.net
 W. Long and K. K. Chin, “Dual material gate field effect transistor
(DMGFET),” in IEDM Tech. Dig., 1997, pp. 549–552.
 S. Tiwari, J. J.Welser, A. Kumar, and S. Cohen, “Straddle-gate
transistors: High Ion/Ioff transistors at short gate lengths,” in Proc.
DRC Dig., 1999, pp. 26–27.
 Y. S. Pang and J. R. Brews, "Analytical sub threshold surface
potential model for pocket n-MOSFETs," IEEE Trans. Electron
Devices, vol. 49, no. 12, pp. 2209-2216, Dec. 2002.
 S.Kolberg T. A.Fjeldly, “2D Modeling of nanoscale
DGSOIMOSFETs in and near the sub threshold regime”, J.
Comput.Electron, vol. 5,pp. 217-222, 2006.

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 REFERENCE
 S.Baishya, A.Mallik and C.K.Sarkar,“A sub threshold surface
potential model for short-channel MOSFET taking into account the
varying depth of channel depletion layer due to source and drain
junctions”, IEEE Trans. Electron Devices, vol. 53,pp. 507-514, Mar.
2006.
 Y. Tsividis, Operation and Modeling of the MOS Transistor,
2nded.New York: McGraw-Hill, 1999.
 B. Yu, C. H. Wann, E. D. Nowak, K. Noda, and C. Hu, "Short
channel effect improved by lateral channel-engineering in deep sub
micrometer MOSFETs," IEEE Trans. Electron Devices, vol. 44,pp.
627-634, Apr. 1997.[15] Y. Tsividis, Operation and Modeling of the
MOS Transistor, 2nded.New York: McGraw-Hill, 1999
 SILVACO International 2000, ATLAS: 2-D Device Simulation
Software.

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