The Microprocessor and its Architecture

The Intel 8086, 80X86, and Pentium Family

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 Contents
• Internal architecture of the Microprocessor:
– The programmer’s model, i.e. the registers model
– The processor (organization) model
• Memory addressing with segmentation
- In the real mode
- In the protected mode
• Memory addressing with paging

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Objectives for this Chapter
• Describe the function and purpose of program-
visible registers
• Describe the Flags register and the purpose of
flag bits
• Describe how memory is accessed using
segmentation in both the real mode and the
protected mode
• Describe the program-invisible registers
• Describe the structures and operation of the
memory paging mechanism
• Describe the organizational processor model
• Briefly review the evolution of the 80X86
architecture

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 The Intel Family Addressable
Memory, bytes
= 2A

(A)

 (1978)

Microcontrollers)

 (2000)

≈ Increase Increase

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 Programming
Model
General Purpose
Registers

Special Purpose
Registers

Segment
80386 and above:
Registers
-32-bit registers (except seg. regs.)
-Two additional segment registers:F,G

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 General-Purpose Registers
• The top portion of the
programming model contains the
general purpose registers:
EAX, EBX, ECX, EDX, EBP, ESI,
and EDI
• Can carry both Data & Address
offsets
• Although general in nature, each
has a special purpose and name:
• EAX – Accumulator
Used also as AX (16 bit),
AH (8 bit), and AL (8 bit)
• EBX – Base Index often used to
address memory (BX, BH, and BL)

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 General-Purpose Registers
(continued)
• ECX – count, for shifts,
rotates, and loops (CX, CH,
and CL)
• EDX – data, used with
multiply and divide (DX,
DH, and DL)
• EBP – base pointer used to
address stack data (BP)
• ESI – source index (SI) for
memory locations, e.g. with
string instructions
• EDI – destination index (DI)
for memory locations
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 Special-Purpose Registers
• ESP, EIP, and EFLAGS
Each has a specific task
– ESP – Stack pointer: Offset to the top of the
stack in the stack segment. Used with
procedure calls (SP)
– EIP – Instruction Pointer: Offset to the next
instruction in a program in the code segment
(IP)
– EFLAGS – indicates latest conditions (state) of
the microprocessor (FLAGS)
Used With
SS
CS

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 EFLAGS

80386DX

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 Determined
The Flags by last
operation
Basic Flag Bits (8086 etc.): Output, Input bits
• C – Carry/borrow from last operation Set/Reset
• P – the parity flag (little used today) explicitly by the
• A – auxiliary flag Half-carry between bits 3 and 4, programmer
used with BCD arithmetic
• Z – zero Some flag bits can be both,
• S – sign e.g. the C flag
• O – Overflow
• D – direction - Determines auto increment/decrement direction
for SI and DI registers with string instructions
• I – interrupt - Enables (using STI) or disables (using CLI) the
processing of hardware interrupts arriving at the INTR input pin
of the processor
• T – Trap - Turns trapping interrupt (for program debugging)
on/off
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 Newer Flag Bits
• IOPL – 2-bit I/O privilege level in protected mode
• NT – nested task
• RF – resume flag (used with debugging)
• VM – virtual mode: multiple DOS programs each
with a 1 MB memory partition in Windows
• AC – alignment check: detects addressing memory
on wrong boundary for words/double words
• VIF – virtual interrupt flag
• VIP – virtual interrupt pending
• ID = CPUID instruction is supported
The instruction gives info on CPU version and manufacturer

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 Segment Registers
Each register points to the start of a segment in memory
• The segment registers are:
– CS (code),
– DS (data),
– ES (extra data. used as destination for some string instructions),
– SS (stack),
– FS, and GS: Additional segment registers on 80386 and above
• Segment registers define the start of a section (segment)
of memory for a program.
• A segment is either:
- 64K (216) bytes of fixed length (real mode), or
- Up to 4G (232) bytes of variable length (protected mode).
• All code (programs) reside in a code segment.

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 Real Mode Memory Addressing
• Used by the DOS operating system
• The only mode available on the 8086-8088:
20 bit address bus  1 MB, 16 bit data bus, 16 bit registers
• Real mode memory is the first 1M (220) bytes of the memory
system (real, conventional, DOS memory) in later processors
• Real mode 20-bit addresses are obtained by combining a
segment number (in a segment register) and an offset address
(in another processor register)
• The segment register address (16-bits) is appended with a 0H
or 00002 (or multiplied by 10H or 16d) to form a 20-bit start of
segment address
• Then the effective memory address (EA) =
this 20-bit segment start address + the 16-bit offset address in
another processor register
• For the 8086, segment length is fixed @ 216 = 64K bytes
(determined by the size of the offset registers)
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 (11MB)
MB

EA (Effective Address) of byte accessed

20-bit (5-byte) 64 KB +
Physical Segment 16-bit each
Memory address

Appended 4 bits (0H)

Segment number
In Segment Register

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 Effective Address Calculations
• EA = segment register (SR) x 10H + offset
(a) SR: 1000H
10000 + 0023 = 10023
(b) SR: AAF0H
AAF00 + 0134 = AB034
(c) SR: 1200H
12000 + FFF0 = 21FF0

Q: Is 3FC81 a valid start address of a segment?

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Overlapping segments

How to detect overlap?

Top of CS:
090F0
FFFF+
190EF

Code should be limited to only

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this portion of the code
segment, to avoid
© 2006 Pearson Education, effects
Upper Saddleof segment
River, overlap
NJ 07458. All Rights Reserved.
 Defaults
Convention Example: EA = CS:[IP]
• Default segment numbers in:
– CS for program (code) Segment number Offset: Literal
– SS for stack in Segment register or in a CPU register
– DS for data
– ES for string (destination) data
• Default offset addresses that go with them:

Segment Offset (16-bit) Offset (32-bit) Purpose

8080, 8086, 80286 80386 and above

CS IP EIP Program

SS SP, BP ESP, EBP Stack

DS BX, DI, SI, 8-bit or 16-bit # EBX, EDI, ESI, EAX ECX,
EDX, 8-bit or 32-bit #
Data

ES DI, with string instructions EDI, with string instructions String

destination
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 Addressing Modes Summary

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 Segmentation: Pros and Cons
Advantages:
• Allows easy and efficient relocation of code and data
• To relocate code or data, only the number in the relevant
segment register needs to be changed
Consequences:
A program can be located anywhere in memory without making
any changes to it (addresses are not absolute, but offsets
relative to start of segments)
Program writer needs not worry about actual memory structure
(map) of the computer used to execute it

Disadvantages:
• Complex hardware and for address generation
• Address computation delay for every memory access
• Software limitation: Program size limited by segment size
(64KB with the 8086)
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 Protected Mode: 80286 and above
• Domain of the Windows operating system
• 32-bit addressing: 4G of memory with 2G for the system
and 2 G for the application
• Protected mode still uses segment and offset addresses, but:
- Segment definition is through a more complex
selector/descriptor mechanism (greater flexibility)
- Offset address: 16-bit (286) or 32-bits (386 and above: e.g.
EIP register)
• Descriptors are placed in descriptor tables in main memory
• Protection is provided by restricting access to memory
segments through:
- Privilege levels,
- and Access rights

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Protected Mode: 80386 and above (Pentium class)
• The base is a 32-bit address at
which the memory segment starts
• The limit is a 20-bit number. When
added to the base, it addresses the
last location in the segment
• The limit has a modifier bit called
Granularity (G). If G=0: no change
• If G=1, append limit with FFFH, i.e.
segment size is multiplied by 4K
• With limit specifying 1 MB
segments and G=1 (i.e. 4K
multiplier): Max Segment size =
4K x 1 MB = 4 GB
• With 16K segments like this, the
system can address 16K x 4 GB =
64 TB (not necessarily all will be in
physical memory)

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Organizational Model of the Processor
- Functional aspects- how the processor actually functions
- Internal organization is determined by functionality required
Two main tasks for the microprocessor in a system:
1. Interface with external peripherals
2. Execute instructions
External Buses
Control bus

Microprocessor-based
System; e.g. a microcomputer
Memory I/O Devices
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 The 8086 processor model (Organization)
• Early pipelining attempts
• Two main functional units:
- The Bus Interface Unit (BIU)
- The Execution Unit (EU)
• The BIU generates memory and I/O addresses for reading code
and transferring data to/from the processor
• The EU takes code and data from the BIU, executes the
instructions, and stores results in the general purpose registers

• Pipelined architecture:
Two, hopefully independent operations, are executed at the
same time by two separate units:
- Fetch by the BIU
- Execute by the EU
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 & Control
External µ p busses

The 8086 processor model FIFO

Instruction/Operand Queue
erfacing: (BIU) BIU fills it
by fetches
Generate all timing & control from
signals for reads, writes, etc. memory
Synchronize data transfers
With all system modules

EU empties it
xecution: (EU) by executing
instructions
Recognize, decode, and
execute fetched program
instructions

ALU

Has no direct interaction

With external
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Intel Microprocessors, 7e EU BIU
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 The 8086 processor model
Non-pipelined 
b. Start fetching at
2. Fetch Wasted fetches the correct target
operand after a Jump inst. location

Pipelined
(8086)

a. Oops! Turned c. Execute

1. Operand 3. Execute
Fetch-Execute Overlap not in Queue
out to be a Jump at last!
instruction!
* = Wasted Fetches and Executes (inefficiency)
RISC & Modern architectures:
• Reduce fetches from memory
Common Scenarios that cause pipeline (operate mostly on registers)
inefficiency:
• Speed up memory fetches (cache)
• Operand is not in queue • Use small instructions (both in
• Jump or branch instructions
length and in execution time)
• Long-executing instructions: • Finer pipeline stages (super
pipelined- 486)
e.g. 83 clock cycles for execution vs. 4
cycles for a fetch. • Multiple pipelines (superscalar- P5)
BIU fills the buffer and waits idly! • Predict how the jump will go
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 Evolution of the 80X86 Intel Processors

2-stage
0.25:1
pipelining
1 execution
unit

0.5:1

Super pipelining 5-stage

pipelining

Super scalar 2 execution

units
5-stage
pipelining
Increase

Pentium Pro, Pentium II, III

3 execution
units
12-stage
pipelining
Multi-core Architecture;
e.g. Itanium® 2
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