Chapter 1

Introduction to Microprocessor &

Microcomputers

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 What is microprocessor ?
•Microprocessor is multipurpose programmable integrated logic
circuit.
•It is used as central processing unit (CPU) of a general purpose
microcomputer system.

Microcomputer is a computer system which uses a microprocessor as

its CPU.

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General architecture of a microcomputer
system

Memory
Primary Memory
Secondary

Program Data Memory

Input MPU Output

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Evolution of intel microprocessor
Architecture
The 4-bit processors

Intel 4004: first single-chip microprocessor

•Introduced November 15, 1971
•Clock rate 740 kHz
•0.07 MIPS
•Bus Width 4 bits (multiplexed address/data due to limited pins)
•Number of Transistors 2,300 at 10 µm
• Addressable memory 640 bytes
• Program memory 4 KB
•PMOS
•Originally designed to be used in calculator

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The 8-bit processors

Intel 8008: One of the earliest Commercial  Microprocessors.

• Introduced April 1, 1972

• Clock rate 500 kHz (8008–1: 800 kHz)
• 0.05 MIPS Bus Width 8 bits (multiplexed address/data )
• Enhancement load PMOS logic
• Number of Transistors 3,500 at 10 µm
• Addressable memory 16 KB
• Typical in early 8 bit microcomputers, general calculators, bottling
machines
• Developed in tandem with 4004
• Originally intended for use in the Data point 2200 microcomputer and
calculator.
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8-bit processors continude…

Intel 8080:

• Introduced April 1, 1974

• Clock rate 2 MHz (very rare 8080B: 3 MHz)
• 0.64 MIPS
• Bus Width 8 bits data, 16 bits address
• Enhancement load NMOS logic
• Number of Transistors 6,000
• Assembly language downwards compatible with 8008.
• Addressable memory 64 KB
• Up to 10X the performance of the 8008
• Used in the Altair 8800, Traffic light controller, cruise missile

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8-bit processors continude…

Intel 8085 :

• Introduced in 1976
• Clock rate 3 MHz
• 0.37 MIPS
• Bus Width 8 bits data, 16 bits address
• Depletion load NMOS logic
• Number of Transistors 6,500 at 3 µm
• Binary compatible downwards with the 8080.
• Used in Toledo scales. Also was used as a computer peripheral
controller – modems, hard disks, printers, etc...
• High level of integration, operating for the first time on a single 5
volt power supply, from 12 volts previously.

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The 16-bit processors: origin of x86
Intel 8086/8088:
• Introduced June 8, 1978
• Clock rates:
4.77 MHz with 0.33 MIPS
8 MHz with 0.66 MIPS

• The memory is divided into odd and even banks. It accesses both the banks
simultaneuosly in order to read 16 bit of data in one clock cycle.

• Bus Width 16 bits data, 20 bits address

• Number of Transistors 29,000 at 3 µm

• Addressable memory 1 megabyte

• Up to 10X the performance of 8080 (typically lower)

• Used in portable computing, and in the IBM PS/2 Model 25 and Model 30.
Also used in the AT&T PC6300 / Olivetti M24. 8
16-bit processors………
8088
• Introduced June 1, 1979
• Clock rates:
– 4.77 MHz with 0.33 MIPS
– 8 MHz with 0.75 MIPS
• Internal architecture 16 bits
• External bus Width 8 bits data, 20 bits address
• Number of Transistors 29,000 at 3 µm
• Addressable memory 1 megabyte
• Identical to 8086 except for its 8 bit external bus (hence an 8 instead of
a 6 at the end)
• Used in IBM PCs and PC clones

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16-bit processors………
80186
Introduced 1982
Clock rates : 6 MHz with > 1 MIPS
Number of Transistors 29,000 at 2 µm
Included two timers, a DMA controller, and an interrupt controller on
the chip in addition to the processor (These were at fixed addresses which
differed from the IBM PC, making it impossible to build a 100% PC-
compatible computer around the 80186.)
Added a few opcodes and exceptions to the 8086 design; otherwise
identical instruction set to 8086 and 8088.
Used mostly in embedded applications – controllers, point-of-sale
systems, terminals, and the like
Used in several non-PC-Compatible MS-DOS computers.
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16-bit processors………
80286:
Introduced February 1982
• Clock rates:
6 MHz with 0.9 MIPS
8 MHz, 10 MHz with 1.5 MIPS
12.5 MHz with 2.66 MIPS
16 MHz, 20 MHz and 25 MHz available
• Bus Width: 16 bit data, 24 bit address.
• Included memory protection hardware to support multitasking
operating systems with per-process address space
• Number of Transistors 134,000 at 1.5 µm
• Addressable memory 16 MB (16 MB)
• Added protected-mode features to 8086 with essentially the
same instruction set
• 3-6X the performance of the 8086
• Widely used in IBM-PC AT and AT clones contemporary to it
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32-bit processors
80386 Range:
• Introduced October 17, 1985
• Clock rates:
– 16 MHz with 5 to 6 MIPS
– 20 MHz with 6 to 7 MIPS, introduced in 1987
– 25 MHz with 8.5 MIPS, introduced in 1988
– 33 MHz with 11.4 MIPS introduced April 10,
1989
• Bus Width 32 bit data, 32 bit address
• Number of Transistors 275,000 at 1 µm
• Addressable memory 4 GB
• Virtual memory 64 TB
• Used in Desktop computing

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80486 range
• Introduced April 10, 1989
• Clock rates:
– 25 MHz with 20 MIPS
– 33 MHz with 27 MIPS introduced May 7, 1990
– 50 MHz with 41 MIPS introduced June 24, 1991
• Bus Width 32 bits
• Number of Transistors 1.2 million at 1 µm; the 50 MHz was at 0.8 µm
• Addressable memory 4 GB
• Virtual memory 1 TB
• Level 1 cache of 8 KB on chip
• Math coprocessor on chip
• Used in Desktop computing and servers

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Pentium

• Introduced March 22, 1993

• Clock rates:
– 75 MHz with 53 MIPS
– 100 MHz with 70.7 MIPS
• Number of Transistors 1.6 million at 0.6 µm
• Bus width 32 bits
• Addressable memory 4 GB

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Microprocessor Performance: MIPS and iCOMP

•MIPS-Million Instruction Per

Second.
•Dry stone program

•iCOMP- Intel
Comparative
Microprocessor
Performance index ratings

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Reprogrammable microprocessors
General purpose microcomputers
•8086/8088,
•80286,
• 80386,
• 80486,
• Pentium processor,

Embedded microprocessors
Special purpose microcomputers
•8080
•8048/ 8051,
•80186 / 80188,
• 80C186xl,
• 80386Ex,
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17
 Chapter 2

8086/8088 Microprocessor
Architecture

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 8086 Microprocessor Architecture

Bus Interfacing Unit (BIU)

•External bus operation.
•Instruction and data acquisition
•Instruction queuing.
•Address generation.
Execution unit (EU)
•Decoding and execution of
instructions
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 Software model of 8086/8088 Microprocessor
MPU Eternal memory
address space
IP (16-bit) (1MB)
0000016
Input/output
CS (16-bit) address space
DS (16-bit) (64KB)
Code Segment
SS (16-bit) (64 Kbytes) 000016
ES (16-bit)

AH AL AX
Data Segment
BH BL BX (64 Kbytes)
CH CL CX
DH DL DX
Stack Segment
SP(16-bit) (64 Kbytes)
BP(16-bit)
SI(16-bit)
Extra Segment FFFF16
DI(16-bit) (64 Kbytes)
SR (16-bit) FFFFF16
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 Memory address space and Data organization
Memory
address space
•8086 MP supports 1MB(1,048,576 bytes) of External Memory of 8086

•Memory In 8086 based microcomputer is organized as 8-bit byte, FFFFF

not as 16-bit word. FFFFE

•Individual bytes of data stored at consecutive addresses over FFFFD

address range 0000h to 0FFFFFh. FFFFC
•8086 can access any two consecutive bytes as a word of data.
-in this case the lower addressed byte is the least significant byte of
the word, & the higher addressed byte is its most significant byte.
Memory 00002
Ex: Data word 1234h
00001
00002 00
00000
00001 12
00000 34

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Storing a word of data in
memory
 Aligned and misaligned data words

• A word of data stored at an even • A word of data stored at an odd

address boundary such as 00000h address boundary such as 00001h ,
,00002h and so on, said to be 00003h and so on, said to be
aligned word Misaligned word

EX: EX:
Memory Memory

Address Address
00003 00 00003 00
00002 00 00002 12
00001 12 00001 34
00000 34 00000 00

Aligned word of data in Misaligned word of data

memory in memory

Data word 1234h is stored @ address Data word 1234h is stored @ address
00000h 00001h
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 Data Types
Integer data Type:

• Unsigned integer:
Unsigned word integer: 0 to 65,535 (0 to 216 -1)
Unsigned byte integer: 0 to 255 (0 to 28 -1)

• Signed integer:
Signed word integer: 32,767 to -32,768 (215 -1 to - 215 )
Signed byte integer: 127 to -128 (27-1 to -27)

BCD numbers:
• Unpacked BCD ex. 0000 0101BCD 05

• Packed BCD ex. 0110 0101BCD 65

ASCII: (American Standard Code for Information Interchange) 23

 Segment Register and Memory Segments

• There are four 16-bit segment registers in 8086 MP

0000016

Code Segment
(64 Kbytes)

CS (16-bit)
Data Segment
DS (16-bit) (64 Kbytes)
SS (16-bit)
ES (16-bit)
Stack Segment
(64 Kbytes)

Extra Segment
(64 Kbytes) 24
FFFFF16
 Dedicated Reserved and General use memory

RESERVED
For Future FFFFFH

products FFFFCH
FFFFBH
FFFF0H
FFFEFH

DEDICATED Open
RESERVED
for Hardware reset
jump instruction To store
pointer for
80H
user defined
7FH
interrupts
14H
13H

DEDICATED 0H

To store pointer for

internal interrupts

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Instruction pointer. (IP)

• IP is also 16-bit in length and identifies the location of the next word of
instruction code to be fetched from current code segment of memory
• It is similar to program counter
• It contains the offset of the next word of instruction code instead of
address.
• The offset in IP is combined with the current value in CS to generate
the 20-bit address.
• This is because IP and CS are 16-bit in length, but 20-bit address is
needed to access memory.
• Therefore the value of the address for the next code access is often
denoted as CS:IP.

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Data registers

• AX – Accumulator
• BX – Base register
• CX – Count register
• DX – Data register

Pointer and index registers.

• SP – Stack pointer
• BP – Base pointer
• SI – Source index
• DI – Destination index

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Status register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- - - - OF DF IF TF SF ZF - AF - PF - CF

Status flags
•CF – Carry flag: Is Set when there is carry out or barrow in from most
significant bit of the result during the execution of instruction, other wise CF is reset.
•PF – Parity flag: Is Set when result produced by the execution of the instruction
has even parity, other wise PF is reset.
•AF – Auxiliary carry: AF is set when there is carry out or barrow in from lower
nibble to higher nibble, during the execution of instruction, other wise AF is reset.
• ZF – Zero flag: ZF is set if result produced by the execution of instruction is zero,
other wise ZF is reset.
•SF – Sign flag: MSB of the result is copied into SF.
•OF – Over flow flag: when OF is set it indicates signed result is out of
range. If the result is not out of range, OF remains reset.
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Control Flags:

• TF – Trap flag: TF is set 8086 goes into the single step mode of operation.
• IF – Interrupt flag :IF is set it recognize the maskable interrupt at its
interrupt input pin (INT). When IF is reset requests at INT are ignored and
maskable interrupt is disabled.
• DF – Direction flag : Logic level of DF determines the direction in which
string operations will occur.
When it is set the string automatically decrements the address. Therefore
string the string data transfers proceed from high address to low address.
When it is reset the string automatically increments the address. Therefore
string the string data transfers proceed from low address to high address.

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Generating a Memory address
15 0
Offset Value Offset

15 0
Segment register 0000 Segment
address

Adder

20 0
20 – bit Physical memory address

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 The Stack
• Stack is a block of memory.
• It is used for temporary storage of information such as
data and address.

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 Input /Output address space
FFFFH

• 8086 has 64K bytes I/O address space

• The I/O address space is the place where
Open
I/O interfaces, such as printer and monitor
ports are implemented.

100H
FFH Reserved
F8H
F7H
Open

00H

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