a b ) Von Neumann architecture

3.3.3 Computer architecture 1

Objectives

a. describe classic Von Neumann architecture,

identifying the need for, and the uses of,
special registers in the functioning of a
processor;
b. describe, in simple terms, the
fetch/decode/execute cycle, and the effects
of the stages of the cycle on specific
registers;

3.3.3 Computer architecture 2

Von Neumann Architecture
 John Von Neumann introduced the idea of
the stored program.
 Previously data and programs were stored in
separate memories.
 Von Neumann realised that data and
programs are indistinguishable and can,
therefore, use the same memory.

3.3.3 Computer architecture 3

 The Von Neumann architecture uses a single processor
which follows a linear sequence of fetch-decode-execute.
 The processor has to use special registers which are used to
control the fetch-execute cycle.
 A register is an area that is used to store data

3.3.3 Computer architecture 4

Activity
 Create a table of the registers and their
functions.
 http://en.wikibooks.org/wiki/A-level_Computing/Print_version#Registers

Register Function
 Fetch Execute Cycle
Fetch
n The address that is in the program counter (PC) is copied into the
memory address register (MAR).
n The PC is incremented by 1.
n Copy the contents of the MAR into the memory data register (MDR).
n Copy the contents in the MDR into the current instruction register (CIR).
Decode
 Decode the instruction that is in the CIR.
 If the instruction is a jump instruction then
 Load the address part of the instruction into the PC
 Reset by going to step 1.

Execute
 Execute the instruction.
 Reset by going to step 1

NB: Another name for the MDR is Memory buffer Register (MBR)

3.3.3 Computer architecture 6

Activity

3.3.3 Computer architecture 7

Watch this movie

 http://www.teach-ict.com/as_as_computing/oc
r/H447/F453/3_3_3/fetch_execute_cycle/mini
web/pg4.htm

3.3.3 Computer architecture 8

Features of a Von Neumann Machine

• The Control Unit

Memory fetches instructions
from memory
• decodes them and
synchronises the
operations before
sending signals to
other parts of the
computer.
• The central processor contains the arithmetic-logic unit and control unit.
• The arithmetic-logic unit (ALU) is where data is processed.

• The Accumulator is in the arithmetic unit

• The Program Counter and the Current Instruction Registers are in the control
unit
• Memory Data Register and Memory Address Register are in the processor.

3.3.3 Computer architecture 9

Exam Questions

Extra Reading – OCR Computing page 149

3.3.3 Computer architecture 10

3.3.3 Computer architecture 11
Summary

 http://studyspace.student.stanmore.ac.uk/file.
php/66/333_Computer_Architecture/fde.htm

 http://studyspace.student.stanmore.ac.uk/file.
php/66/333_Computer_Architecture/vonneum
ann.htm
Activity
1. Further Reading
 http://www.teach-ict.com/as_as_computing/o
cr/H447/F453/3_3_3/vonn_neuman/miniweb/
index.htm
 www.it.jcu.edu.au/Subjects/cp1300/resource
s/lectnotes/system/fde.html