Motorola 68000 Interrupt System Three Interrupt control Lines > IPL0, IPL1, and IPL2.

These lines provides for seven interrupt priority levels. The 68000 has three output status lines FC2, FC1, and FC0, called function code pins. These lines tell external devices whether user data/program or supervisor data/program is being addressed. These lines can be decoded to provide user or supervisor program data and interrupt acknowledge.

as shown in Table the FC2, FC1, and FC0 pins can be used to partition memory into four functional areas: user data memory, user program memory, supervisor data memory, and supervisor program memory.

Each memory partition can directly access up to 16 MB, and thus the 68000 can be made to directly address up to 64 MB of memory. This is shown

On the above table, when all three FC outputs are all 1, the 68000 is signaling an Interrupt Acknowledge.

As shown in this figure the FC outputs are used to generate the VPA signal which tells the 68000 how to process an interrupt request.

these interrupt sources fall into the category of software.

When the 68000 receives the number 101, it checks its status register to see whether such an interrupt is currently allowed. If not, then the 101 is temporarily ignored. If it is allowed, then the 68000 completes the current instruction and then begins exception processing. Exception Processing on the 68000(either hardware or software. The 68000 begins by stopping the current program, switching to supervisor mode(if not already in it), and then outputting a 111 on the FC outputs to acknowledge the interrupt. At this point, it needs to know where to find the ISR which is supposed to process the interrupt.

There is room in low memory, between locations $0 and $3FF, for up to 256 exception vectors, which are pointers to interrupt service routines. These vectors would normally be placed there by some program, though they could also be in ROM. When the 68000 outputs the 111 on the FC outputs, its also outputs the number of the interrupt on the A2-A0 address lines. One of two things can now happen in a typical system. 1. The interrupting device can tell the 68000 which vector to use to find the ISR. it would do this by placing a high on the VPA line, and putting the vector (an eight-bit number between 0 and 255) on data bus lines D7 through D0.

2. External circuitry can place a low on the VPA line, in which case the 68000 will automatically choose one of seven vectors, depending on the interrupt level. Since the 68000 choose its own interrupt vector, this is called auto-vectoring. As shown in the previous figure, U37b automatically sends a low to the VPA pin of the 6800 as soon as it receives three highs on the FC lines, and so the SK68K uses auto-vectoring to choose a hardware interrupt vector.

80286 INTERRUPT SYSTEM MASKABLE INTERRUPT(INTR) The 80286 provides a maskable hardware interrupt request pin, INTR. Software enables this input by setting the interrupt flag bit(IF) in the flag word. All 224 user-defined interrupt sources can share this input. yet they can retain by the CPU during the interrupt acknowledge sequence.

Further maskable interrupts are disabled while servicing an interrupt by resetting the IF bit as part of the response to an interrupt or exception. The save flag word will reflect the enable status of the process prior to the interrupt. Until the flag word is restored to the flag register, the interrupt flag will be zero unless specifically set. The interrupt return instruction includes restoring the flag word, thereby restoring the original status of IF.

Non-Maskable interrupt request (NMI) A Non-maskable interrupt input (NMI) is also provided. NMI has higher priority than INTR. A typical use of NMI would be to activate a power failure routine. The activation of this input causes an interrupt with an internally supplied vector value of 2. No external interrupt acknowledge sequence is performed.

While executing the NMI servicing procedure, the 80286 will service neither further NMI requests, INTR requests, nor the processor extension return(IRET) instruction is executed or the CPU is reset. If NMI occurs while currently servicing after executing the first IRET instruction. IF is cleared at the beginning of an NMI interrupt to inhibit INTR interrupts.

SINGLE STEP INTERRUPT The 80286 has an internal interrupt that allows programs to execute one instruction at a time. It is called the single step interrupt and is controlled by the single step flag bit(TF) in the flag word. Once this bit is set, an internal single step interrupt will occur after the next instruction has been executed. The interrupt clears the TF bit and uses an internally supplied vector of 1. The IRET instruction is used to set TF bit and transfer control to the next instruction to be single stepped.