ARM Instruction Set

Introduction:


Classification of an instruction by its class e.g. - Data processing instructions * MOV instruction. * Arithmetic instruction * Logical instruction * Comparison instruction * Multiply instruction - Branch instructions - Load- store instructions - Software interrupt instruction - Program status register instruction

Data processing instruction:

Note:
1.

One of the operands is processed by barrel shifter. MOV Instruction: Syntax: {MOV}{<cond>}{S} Rd, N (N = Rm or a constant )

2. Instruction with suffix S, only updates flags.



MOV MVN

Move a 32 bit value into a register Rd = N Move the Not of the 32 bit value into a register Rd = ~N

Barrel Shifter:
Rn
Rm

BS
Result N

ALU
Rd


It is for preprocessing of one of the operands of some data processing instructions. For this processing additional cycles are not required. Due to this preprocessing, system performance is improved fast multiply and divide by 2 is possible.

 

Barrel Shift operations:

LSL LSR ASR ROR RRX

Logical shift left Logical shift right Arithmetic shift right Rotate right Rotate right extended

Barrel shift operation syntax for data processing instructions:

Immediate Register Logical shift left by immediate Logical shift left by register Logical shift right by immediate Logical shift right by register Arithmetic shift right by immediate Arithmetic shift right by register Rotate right by immediate Rotate right by register Rotate right with extend #immediate Rm Rm, LSL # shift_imm Rm, LSL # Rs Rm, LSR # shift_imm Rm, LSR # Rs Rm, ASR #shift_imm Rm, ASR Rs Rm, ROR #shift_imm Rm, ROR #Rs Rm, RRX

Arithmetic Instructions:
Syntax: <instruction>{<cond>}{S} Rd, Rn, N * Meaning Rd = Rn + N * N is the result of shift operation. Examples: ADC Add two 32-bit values & carry. ADD Add two 32-bit values. RSC Reverse subtract of two 32-bit values with carry. SBC Subtract with carry two 32-bit values SUB Subtract two 32-bit values

Rd=Rn+N+CY Rd=Rn+N Rd=N-Rn-CY Rd=Rn-N-CY Rd=Rn-N

RSB Reverse subtract of two 32-bit values. Rd=N-Rn

Logical operations:
Syntax: <instruction>{<cond>}{S} Rd, Rn, N AND ORR EOR BIC Logical bit-wise AND of two 32-bit values Logical bit-wise OR of two 32-bit values Logical bit-wise EXOR of two 32bit values Logical bit clear (AND NOT) Rd = Rn & N Rd = Rn | N Rd = Rn ^ N Rd = Rn & ~N

Note: Logical instructions updates flags only if S is attached to the Instruction

Comparison Instructions:
Syntax: <instruction>{<cond>} Rn, N Examples:

CMN CMP TEQ TST

Compare negated Compare

Flags set as a result of Rn + N Flags set as a result of Rn - N

Test for equality of two 32-bit Flags set as a result values of Rn ^ N Test bits of a 32-bit value Flags set as a result of Rn & N

Note:Flags are updated without S suffix.

Multiply Instructions:
Syntax: MLA {<cond>} {S} Rd, Rm, Rs, Rn MUL {<cond>} {S} Rd, Rm, Rs MLA MUL Multiply & accumulate Multiply Rd = (Rm*Rs) + Rn Rd = Rm*Rs

Syntax: <instruction> {<cond>} {S} RdLo, RdHi, Rm, Rs

SMLAL Signed multiply accumulate long SMULL Signed multiply long UMLAL Unsigned multiply accumulate long UMULL Unsigned multiply long {RdHi,RdLo}={RdHi,RdLo} + Rm*Rs {RdHi,RdLo}=Rm*Rs {RdHi,RdLo}={RdHi,RdLo} + Rm*Rs {RdHi,RdLo}=Rm*Rs

Branch instructions:
Syntax: 1. B{<cond>} label 2. BL{<cond>} label 3. BX{<cond>} Rm 4. BLX{<cond>} label/Rm

B BL BX

Branch Branch with link Branch exchange

PC = label PC = label, LR = next instruction address PC = Rm & 0xfffffffe, T= Rm & 1 PC = label , T = 1 PC = Rm & 0xfffffffe, T = Rm & 1 LR = next instruction address

BLX Branch exchange with link

Note: Label is signed PC relative address and must be within approximately 32 MB of the branch instruction.

Load Store instructions:



Load-Store instructions transfer data between memory and processor registers. Three types of instructions - single register transfer instructions. - multiple register transfer instructions - swap instructions.

Byte, half word and word transfer is possible.

Single register transfer:

Syntax: <LDR/STR> {<cond>}{B} Rd, addressing_1 LDR{<cond>} {SB|H|SH} Rd, addressing_2 STR{<cond>} {H} Rd, addressing_2
LDR STR LDRB STRB LDRH STRH LDRSB LDRSH Load word into a register Save byte or word from a register Load byte into a register Save byte from a register Load half-word into a register Save half-word into a register Load signed byte into a register Load signed half-word into a register Rd<-mem32[address] Rd->mem32[address] Rd<-mem8[address] Rd->mem8[address] Rd<-mem16[address] Rd->mem32[address] Rd<-signExtend (mem8/16[address])

Multiple Register Transfer:

With single instruction multiple register can be transferred from/to memory.  System efficiency improves but increase in interrupt latency. Syntax:


<LDM/STM>{ <cond>}<addressing mode>Rm{!}, <registers>{^} Addressing modes: IA Increment After. IB Increment Before. DA Decrement After. DB Decrement Before Examples: LDMIA R0!, {R1 R3}, STMDB R0!, {R1, R5-R8} more

Stack:


A stack is an area of memory which grows as new data is pushed onto the top of it, and shrinks as data is popped off the top. Two pointers define the current limits of the stack.  A base pointer used to point to the bottom of the stack (the first location).  A stack pointer used to point the current top of the stack.
PUSH {1,2,3}
SP 3 2 1 SP BASE 2 1

POP
Result of pop = 3

SP BASE

BASE

Traditionally, a stack grows down in memory, with the last pushed value at the lowest address. The ARM also supports ascending stacks, where the stack structure grows up through memory. The value of the stack pointer can either:


Point to the last occupied address (Full stack) and so needs pre-decrementing (ie before the push)

Point to the next occupied address (Empty stack) and so needs post-decrementing (ie after the push)

Stack Operation:
Addressing Description mode FA FD EA ED Full ascending Full descending Empty ascending Empty descending POP = LDMFA LDAFD LDMEA LDMED Push = STMFA STMFD STMEA STMED LDM LDMDA LDMIA LDMDB LDMIB STM STMIB STMDB STMIA STMDA PUSH Instructions

POP Instructions

Addressing Description mode FA FD EA ED Full ascending Full descending Empty ascending Empty descending

STMED sp!, {r0,r1,r3-r5}

STMFA sp!, {r0,r1,r3-r5}

STMEA sp!, {r0,r1,r3-r5}

0x418
SP r5 r4 r3 r1 r0 SP r5 r4 r3 r1 r0

Old SP

r5 r4 r3 r1 r0

Old SP

Old SP

0x400

SP

0x3e8

SWAP Instructions:


Atomic operation of a memory read followed by a memory write which moves byte or word quantities between registers and memory. Syntax:


SWP{<cond>}{B} Rd, Rm, [Rn]

1 temp 2 Memory Rm Rd 3

Rn

SWI Instruction:
It causes software interrupt exception CPU branches to vector address 0x00000008.  This instruction is used to call O.S. routines. Syntax: SWI {<cond>} SWI number ( e.g. SWI 0x18) Events sequence after execution: * lr_svc = address of an instruction following the SWI. * spsr_svc = CPSR * PC = 0x8 * CPSR mode SVC, CPSR_I = 1 (mask IRQ interrupt)  The SWI number specifies what function to be executed


The Procedure: execution of SWI

User program Vector table 0x00000000 ISR SINT: Find out SWI number & branch To specific function

SWI xyz

0x00000008 B SINT

xyz

lmn

abc

Program Status Register Instructions:

 

It is for reading/writing from/to program status register. Two major instructions, * MRS transfer contents of CPSR/SPSR to register. * MSR transfer contents of register to CPSR/SPSR.

Syntax: MRS {<cond>} Rd, <cpsr/spsr> MSR {<cond>} <cpsr/spsr>_<field>,Rm MSR {<cond>} <cpsr/spsr>_<field>, #immediate Note: The component field specified in the syntax relates to the filed specifies in the CPSR/SPSR,( e.g. c, x, f and s)

Test No: 1
1. 2. 3.

Duration:10 minutes

What is the function of Sign extended block? Why do User/System mode not have SPSR? What is Undefined operating mode? Explain in brief with one example.

4.

What is the exact difference between privileged and unprivileged mode?

5.

Why is FIQ faster than IRQ?

Note: All questions carry equal marks

Coprocessor Instructions:


The ARM architecture supports 16 coprocessors The most common Coprocessors * System Coprocessor used to control on-chip functions such as the cache and MMU on the ARM720. * A floating point ARM coprocessor etc.

Each coprocessor instruction set occupies part of the ARM instruction set. There are three types of coprocessor instruction
  

Coprocessor data processing Coprocessor (to/from ARM) register transfers Coprocessor memory transfers (load and store to/from memory)

Assembler macros can be used to transform custom coprocessor mnemonics into the generic mnemonics understood by the processor. A coprocessor may be implemented
  

in hardware in software (via the undefined instruction exception) in both (common cases in hardware, the rest in software)
For example, a Floating point multiply, which multiplies the contents of two registers and stores the result in a third register

The operation is performed only on internal coprocessor state



Coprocessor data operations:



These operations are completely internal to the Coprocessor and cause a state change in the Coprocessor registers.
28 27 24 23 20 19 16 15 12 11 8 7 5 4 3 0

Binary format:
31

cond

1110 Cop1 CRn

CRd

CP#

Cop2

CRm

Assembler format: CDP{<cond>} <cp#>, <Cop1>, CRd, CRn, CRm {<Cop2>} Examples: CDP p2, 3, C0, C1, C2 p3, 6, C1, C5, C7, 4 CDPEQ

Coprocessor Register Transfer



These instructions allow an integer generated in a coprocessor to be transferred directly into a ARM registers.

Assembler format: MRC {<cond>} <CP#>, <Cop1>, Rd, CRn, CRm {<Cop2>} ;Move to ARM registers from Coprocessor. MCR {<cond>} <CP#>, <Cop1>, Rd, CRn, CRm {<Cop2>} ;Move to Coprocessor from ARM registers. Examples: MCR p14, 3, R0, C1, C2

MRCCS p2, 4, R3, C3, C4, 6

Coprocessor Memory Transfer



Theses instructions allow data transfer from/to memory.

Assembler format: LDC|STC {<cond>} {L} <CP#>, CRd, [ Rn, <offset> ] {!} ; the pre-indexed form. LDC|STC {<cond>} {L} <CP#>, CRd, [ Rn], <offset> ;the post-indexed form. L indicates long data type( Coprocessor dependant) Examples: LDC p6, C0, [R1]

STCEQL p5, C1, [R0], #4

Test No. 2


Duration: 10 minutes

Write a block transfer program in assembly language. Block size: 40 bytes. Source block starting address: 0x00001000 Destination block starting address: 0x00002000  What is the contents of R0 register after execution of following program. LDR R0, = 0x00000cd1 LDR R1, = 0x00003344 CMP R0, R1, LSR #2 BEQ stop ADD R0, R0, R1 Stop: B stop