Fundamentals of Digital Test and DFT: Vishwani D. Agrawal

Fundamentals of Digital Test and DFT
Vishwani D. Agrawal
Rutgers University, Dept. of ECE New Jersey
http://cm.bell-labs.com/cm/cs/who/va
January 2003
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Agrawal: Digital Test and DFT
Course Outline

Basic concepts and definitions Fault modeling Fault simulation ATPG DFT and scan design BIST Boundary scan IDDQ test
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VLSI Realization Process

Customers need
Determine requirements
Write specifications
Design synthesis and Verification
Test development
Fabrication Manufacturing test
Chips to customer
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Definitions
Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes. Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.
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Realities of Tests

Based on analyzable fault models, which may not map onto real defects. Incomplete coverage of modeled faults due to high complexity. Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss. Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level.
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Costs of Testing
Design for testability (DFT)
Chip area overhead and yield reduction Performance overhead
Software processes of test Test generation and fault simulation Test programming and debugging Manufacturing test Automatic test equipment (ATE) capital cost Test center operational cost
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Cost of Manufacturing Testing in 2000AD
0.5-1.0GHz, analog instruments,1,024 digital pins: ATE purchase price = $1.2M + 1,024 x $3,000 = $4.272M Running cost (five-year linear depreciation) = Depreciation + Maintenance + Operation = $0.854M + $0.085M + $0.5M = $1.439M/year Test cost (24 hour ATE operation) = $1.439M/(365 x 24 x 3,600) = 4.5 cents/second
Agrawal: Digital Test and DFT 7
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Present and Future*

1997--2001 2003--2006
Feature size (micron) 0.25 - 0.15 0.13 - 0.10 Transistors/sq. cm 4 - 10M 18 - 39M
Pin count Clock rate (MHz) Power (Watts)
100 - 900 200 - 730 1.2 - 61
160 - 1475 530 - 1100 2 - 96
* SIA Roadmap, IEEE Spectrum, July 1999

Method of Testing
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ADVANTEST Model T6682 ATE
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LTX FUSION HF ATE
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VLSI Chip Yield
A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. A chip with no manufacturing defect is called a good chip. Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Yield is denoted by symbol Y. Cost of a chip:
Cost of fabricating and testing a wafer -------------------------------------------------------------------Yield x Number of chip sites on the wafer
Defect Level or Reject Ratio

Defect level (DL) is the ratio of faulty
chips among the chips that pass tests. DL is measured as parts per million (ppm). DL is a measure of the effectiveness of tests. DL is a quantitative measure of the manufactured product quality. For commercial VLSI chips a DL greater than 500 ppm is considered unacceptable.
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Example: SEMATECH Chip

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Bus interface controller ASIC fabricated and tested at IBM, Burlington, Vermont 116,000 equivalent (2-input NAND) gates 304-pin package, 249 I/O Clock: 40MHz, some parts 50MHz 0.45m CMOS, 3.3V, 9.4mm x 8.8mm area Full scan, 99.79% fault coverage Advantest 3381 ATE, 18,466 chips tested at 2.5MHz test clock Data obtained courtesy of Phil Nigh (IBM)
Computed DL
237,700 ppm (Y = 76.23%)
Defect level in ppm
Stuck-at fault coverage (%)

Summary: Introduction

VLSI Yield drops as chip area increases; low yield means high cost Fault coverage measures the test quality Defect level (DL) or reject ratio is a measure of chip quality DL can be determined by an analysis of test data For high quality: DL < 500 ppm, fault coverage ~ 99%
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Fault Modeling
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Why Model Faults?
I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing) Real defects (often mechanical) too numerous and often not analyzable A fault model identifies targets for testing A fault model makes analysis possible Effectiveness measurable by experiments
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Some Real Defects in Chips
Processing defects Missing contact windows Parasitic transistors Oxide breakdown . . . Material defects Bulk defects (cracks, crystal imperfections) Surface impurities (ion migration) . . . Time-dependent failures Dielectric breakdown Electromigration . . . Packaging failures Contact degradation Seal leaks . . .
Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation Semiconductor Devices and Circuits, Wiley, 1981.
Observed PCB Defects

Defect classes Shorts Opens Missing components Wrong components Reversed components Bent leads Analog specifications Digital logic Performance (timing) Occurrence frequency (%) 51 1 6 13 6 8 5 5 5
Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985.

Common Fault Models
Single stuck-at faults Transistor open and short faults Memory faults PLA faults (stuck-at, cross-point, bridging) Functional faults (processors) Delay faults (transition, path) Analog faults For more examples, see Section 4.4 (p. 6070) of the book.
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Single Stuck-at Fault
Three properties define a single stuck-at fault

Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults
c
1 0
Only one line is faulty The faulty line is permanently set to 0 or 1 The fault can be at an input or output of a gate
Faulty circuit value Good circuit value
a b
d e f
s-a-0
0(1) 1(0)
g
1
h i k
Test vector for h s-a-0 fault

Fault Equivalence

Number of fault sites in a Boolean gate circuit = #PI + #gates + #(fanout branches). Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2. If faults f1 and f2 are equivalent then the corresponding faulty functions are identical. Fault collapsing: All single faults of a logic circuits can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset.
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Equivalence Example
sa0 sa1 sa0 sa1 sa0 sa1 Faults in red removed by equivalence collapsing
sa0 sa1
sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1
sa0 sa1 sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1 20 Collapse ratio = ----- = 0.625 32
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Summary: Fault Models
Fault models are analyzable approximations of defects and are essential for a test methodology. For digital logic single stuck-at fault model offers best advantage of tools and experience. Many other faults (bridging, stuck-open and multiple stuck-at) are largely covered by stuck-at fault tests. Stuck-short and delay faults and technologydependent faults require special tests. Memory and analog circuits need other specialized fault models and tests.
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Fault Simulation
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Problem and Motivation
Fault simulation Problem: Given

A circuit A sequence of test vectors A fault model

Fault coverage - fraction (or percentage) of modeled faults detected by test vectors Set of undetected faults Determine test quality and in turn product quality Find undetected fault targets to improve tests
Determine

Motivation
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Fault simulator in a VLSI Design Process

Verified design netlist Fault simulator Verification input stimuli Test vectors
Modeled Remove fault list tested faults Fault coverage ?
Test Delete compactor vectors
Low
Test generator
Add vectors
Adequate Stop
Fault Simulation Scenario
Circuit model: mixed-level

Mostly logic with some switch-level for highimpedance (Z) and bidirectional signals High-level models (memory, etc.) with pin faults Two (0, 1) or three (0, 1, X) states for purely Boolean logic circuits Four states (0, 1, X, Z) for sequential MOS circuits Zero-delay for combinational and synchronous circuits Mostly unit-delay for circuits with feedback
Signal states: logic
Timing:
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Fault Simulation Scenario (continued)
Faults:

Mostly single stuck-at faults Sometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in common use Equivalence fault collapsing of single stuck-at faults Fault-dropping -- a fault once detected is dropped from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosis Fault sampling -- a random sample of faults is simulated when the circuit is large
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Essence of Fault Sim.

Test vectors Fault-free circuit Circuit with fault f1 Comparator Circuit with fault f2 Comparator Circuit with fault fn f2 detected? Comparator f1 detected?
fn detected?
Disadvantage: Much repeated computation; CPU time prohibitive for VLSI circuits Alternative: Simulate many faults together
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Fault Sampling

A randomly selected subset (sample) of faults is simulated. Measured coverage in the sample is used to estimate fault coverage in the entire circuit. Advantage: Saving in computing resources (CPU time and memory.) Disadvantage: Limited data on undetected faults.
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Random Sampling Model

Detected fault
Undetected fault
All faults with a fixed but unknown coverage

(population size)
Random
picking
Np = total number of faults C = fault coverage (unknown)
Ns = sample size Ns << Np c = sample coverage
(a random variable)
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Probability Density of Sample Coverage, c

p (x ) = Prob(x < c < x +dx ) = -------------- e
s (2 p)
1/2
-- -----------2s
2
(x--C )2
2 = C (1 - C) Variance, s ------------
p (x )
Ns
Mean = C
Sampling error
C -3s
C +3s 1.0
Sample coverage
Sampling Error Bounds

|x-C|=3
[ -------------- ] 1/2 N
s
C (1 - C )
Solving the quadratic equation for C, we get the 3-sigma (99.7% confidence) estimate:
4.5 C 3s = x ------- [1 + 0.44 Ns x (1 - x )]1/2 Ns Where Ns is sample size and x is the measured fault coverage in the sample. Example: A circuit with 39,096 faults has an actual fault coverage of 87.1%. The measured coverage in a random sample of 1,000 faults is 88.7%. The above formula gives an estimate of 88.7% 3%. CPU time for sample simulation was about 10% of that for all faults.
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Summary: Fault Sim.

Fault simulator is an essential tool for test development. Concurrent fault simulation algorithm offers the best choice. For restricted class of circuits (combinational and synchronous sequential with only Boolean primitives), differential algorithm can provide better speed and memory efficiency (Section 5.5.6.) For large circuits, the accuracy of random fault sampling only depends on the sample size (1,000 to 2,000 faults) and not on the circuit size. The method has significant advantages in reducing CPU time and memory needs of the simulator.
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Automatic Test-pattern Generation (ATPG)
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Functional vs. Structural ATPG
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Functional vs. Structural (Continued)
Functional ATPG generate complete set of tests for circuit input-output combinations 129 inputs, 65 outputs: 2129 = 680,564,733,841,876,926,926,749, 214,863,536,422,912 patterns Using 1 GHz ATE, would take 2.15 x 1022 years Structural test: No redundant adder hardware, 64 bit slices Each with 27 faults (using fault equivalence) At most 64 x 27 = 1728 faults (tests) Takes 0.000001728 s on 1 GHz ATE Designer gives small set of functional tests augment with structural tests to boost coverage to 98+ %
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Random-Pattern Generation
Flow chart for method Use to get tests for 6080% of faults, then switch to D-algorithm or other ATPG for rest
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Path Sensitization Method Circuit Example

1 Fault Activation 2 Fault Propagation 3 Line Justification
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Try path f h k L blocked at j, since
there is no way to justify the 1 on i D D D 1 0 1 1
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Try simultaneous paths f h k L and
g i j k L blocked at k because D-frontier (chain of D or D) disappears
1 1
D
D D
1
D
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Final try: path g i j k L test found!
0 1
0
D D D
1 1
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Sequential Circuits

A sequential circuit has memory in addition to combinational logic. Test for a fault in a sequential circuit is a sequence of vectors, which

Initializes the circuit to a known state Activates the fault, and Propagates the fault effect to a primary output Time-frame expansion methods Simulation-based methods
Methods of sequential circuit ATPG

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Concept of Time-Frames
If the test sequence for a single stuck-at fault contains n vectors,

Replicate combinational logic block n times Place fault in each block Generate a test for the multiple stuck-at fault using combinational ATPG with 9-valued logic
Vector -n+1 Vector -1 Vector 0
Fault
Unknown or given Init. state
Comb. block
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Timeframe -n+1
State variables
Timeframe -1 PO -1
Timeframe 0 PO 0
Next state
PO -n+1
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An Example of Seq. ATPG
FF1
s-a-1
FF2
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0,1, 1/0, 0/1, 1/X, 0/X, X/0, X/1, X

A 0
s-a-1 0/1 FF1 FF2
Nine-Valued Logic (Muth)

A X
s-a-1 0/X
X/1
0/X FF1 FF2
X X
0/1
X/1
Time-frame -1
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B X
Time-frame 0
0/1
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Seq. ATPG Results

s1423
Total faults Detected faults 1,515 1,414
s5378
4,603 3,639
s35932
39,094 35,100
Fault coverage
Test vectors CPU time HP J200 256MB
93.3%
3,943 1.3 hrs.
79.1%
11,571 37.8 hrs.
89.8%
257 10.2 hrs.
Ref.: M. S. Hsiao, E. M. Rudnick and J. H. Patel, Dynamic State Traversal for Sequential Circuit Test Generation, ACM Trans. on Design Automation of Electronic Systems (TODAES), vol. 5, no. 3, July 2000.
Summary: ATPG

Combinational ATPG is significantly more efficient than sequential ATPG. Combinational ATPG tools are commercially available. Design for testability is essential if the circuit is large (million or more gates) and high fault coverage (~95%) is required.
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Design for Testability
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Definition
Design for testability (DFT) refers to those design techniques that make test generation and test application cost-effective. DFT methods for digital circuits: Ad-hoc methods Structured methods:

Scan Partial Scan Built-in self-test (BIST) Boundary scan Analog test bus
DFT method for mixed-signal circuits:
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Ad-Hoc DFT Methods
Good design practices learnt through experience are used as guidelines:

Design reviews conducted by experts or design auditing tools. Disadvantages of ad-hoc DFT methods:
Avoid asynchronous (unclocked) feedback. Make flip-flops initializable. Avoid redundant gates. Avoid large fanin gates. Provide test control for difficult-to-control signals. Avoid gated clocks. ... Consider ATE requirements (tristates, etc.)
Experts and tools not always available. Test generation is often manual with no guarantee of high fault coverage. Design iterations may be necessary.
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Scan Design
Circuit is designed using pre-specified design
rules. Test structure (hardware) is added to the verified design:

Use combinational ATPG to obtain tests for all
Add a test control (TC) primary input. Replace flip-flops by scan flip-flops (SFF) and connect to form one or more shift registers in the test mode. Make input/output of each scan shift register controllable/observable from PI/PO.
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testable faults in the combinational logic. Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test.
Scan Design Rules

Use only clocked D-type of flip-flops for all state variables. At least one PI pin must be available for test; more pins, if available, can be used. All clocks must be controlled from PIs. Clocks must not feed data inputs of flip-flops.
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Scan Flip-Flop (SFF)

D TC
Logic overhead
Master latch
Slave latch
Q
MUX
SD CK
D flip-flop
CK
Master open Slave open
t
Scan mode, SD selected
TC
Normal mode, D selected
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Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF)

Master latch D Q Slave latch
MCK SCK SD
Logic overhead
Q D flip-flop Normal mode Scan mode t

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MCK TCK MCK TCK SCK
TCK
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Adding Scan Structure

PI Combinational logic PO
SFF
SFF SFF
SCANOUT
TC or TCK SCANIN
2003 Agrawal: Digital Test and DFT
Not shown: CK or MCK/SCK feed all SFFs.

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Comb. Test Vectors
PI SCANIN TC Presen t state
I1
I2 Combinational logic
O1
O2
PO
SCANOUT Next state
S1
S2
N1
N2
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Testing Scan Register
Scan register must be tested prior to application of scan test sequences. A shift sequence 00110011 . . . of length nsff+4 in scan mode (TC=0) produces 00, 01, 11 and 10 transitions in all flip-flops and observes the result at SCANOUT output. Total scan test length: (ncomb + 2) nsff + ncomb + 4 clock periods. Example: 2,000 scan flip-flops, 500 comb. vectors, total scan test length ~ 106 clocks. Multiple scan registers reduce test length.
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Scan Overheads

IO pins: One pin necessary. Area overhead: Gate overhead = [4 nsff/(ng+10nff)] x 100%, where ng = comb. gates; nff = flip-flops; Example ng = 100k gates, nff = 2k flip-flops, overhead = 6.7%. More accurate estimate must consider scan wiring and layout area. Performance overhead: Multiplexer delay added in combinational path; approx. two gate-delays. Flip-flop output loading due to one additional fanout; approx. 5-6%.
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ATPG Example: S5378

Original Number of combinational gates Number of non-scan flip-flops (10 gates each) Number of scan flip-flops (14 gates each) Gate overhead Number of faults PI/PO for ATPG Fault coverage Fault efficiency CPU time on SUN Ultra II, 200MHz processor Number of ATPG vectors Scan sequence length 2,781 179 0 0.0% 4,603 35/49 70.0% 70.9% 5,533 s 414 414 Full-scan
2,781 0 179 15.66% 4,603 214/228 99.1% 100.0% 5s 585 105,662
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Summary: Scan Design
Scan is the most popular DFT technique:
Advantages:

Rule-based design Automated DFT hardware insertion Combinational ATPG

Design automation High fault coverage; helpful in diagnosis Hierarchical scan-testable modules are easily combined into large scan-testable systems Moderate area (~10%) and speed (~5%) overheads Large test data volume and long test time Basically a slow speed (DC) test
Disadvantages:

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Built-In Self-Test (BIST)
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BIST Process
Test controller Hardware that activates self-
test simultaneously on all PCBs Each board controller activates parallel chip BIST Diagnosis effective only if very high fault coverage
Example External XOR LFSR
Characteristic polynomial f (x) = 1 + x + x3 (read taps from right to left)

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Definitions

Aliasing Due to information loss, signatures

of good and some bad machines match Compaction Drastically reduce # bits in original circuit response lose information Compression Reduce # bits in original
circuit response no information loss fully invertible (can get back original response) Signature analysis Compact good machine response into good machine signature.
Actual signature generated during testing, and compared with good machine signature
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Example Modular LFSR Response Compacter
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LFSR seed value is 00000

Multiple-Input Signature Register (MISR)
Problem with ordinary LFSR response compacter: Too much hardware if one of these is put on each primary output (PO) Solution: MISR compacts all outputs into one LFSR Works because LFSR is linear obeys
superposition principle
Superimpose all responses in one LFSR
final remainder is XOR sum of remainders of polynomial divisions of each PO by the characteristic polynomial
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Modular MISR Example
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Built-in Logic Block Observer (BILBO)
Combined functionality of D flip-flop, pattern generator, response compacter, & scan chain Reset all FFs to 0 by scanning in zeros
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Circuit Initialization
Full-scan BIST shift in scan chain seed before starting BIST
Partial-scan BIST critical to initialize all FFs before BIST starts
Otherwise we clock Xs into MISR and signature is

not unique and not repeatable
Discover initialization problems by:
1. Modeling all BIST hardware 2. Setting all FFs to Xs 3. Running logic simulation of CUT with BIST hardware
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Summary: BIST

LFSR pattern generator and MISR response compacter preferred BIST methods BIST has overheads: test controller, extra circuit delay, Input MUX, pattern generator, response compacter, DFT to initialize circuit & test the test hardware BIST benefits: At-speed testing for delay & stuck-at faults Drastic ATE cost reduction Field test capability Faster diagnosis during system test Less effort to design testing process Shorter test application times
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Boundary Scan Standard
IEEE 1149.1
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System Test Logic
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Serial Board / MCM Scan
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Parallel Board / MCM Scan
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Tap Controller Signals
Test Access Port (TAP) includes these signals: Test Clock Input (TCK) -- Clock for test logic

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Can run at different rate from system clock Test Mode Select (TMS) -- Switches system from functional to test mode Test Data Input (TDI) -- Accepts serial test data and instructions -- used to shift in vectors or one of many test instructions Test Data Output (TDO) -- Serially shifts out test results captured in boundary scan chain (or device ID or other internal registers) Test Reset (TRST) -- Optional asynchronous TAP controller reset
Summary: Bound. Scan
Functional test: verify system hardware, software, function and performance; pass/fail test with limited diagnosis; high (~100%) software coverage metrics; low (~70%) structural fault coverage. Diagnostic test: High structural coverage; high diagnostic resolution; procedures use fault dictionary or diagnostic tree. SOC design for testability:

Partition SOC into blocks of logic, memory and analog circuitry, often on architectural boundaries. Provide external or built-in tests for blocks. Provide test access via boundary scan and/or analog test bus. Develop interconnect tests and system functional tests. Develop diagnostic procedures.
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IDDQ Test
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Basic Principle of IDDQ Testing
Measure IDDQ current through Vss bus

Capacitive Coupling of Floating Gates

Cpb capacitance from
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poly to bulk Cmp overlapped metal wire to poly Floating gate voltage depends on capacitances and node voltages If nFET and pFET get enough gate voltage to turn them on, then IDDQ test detects this defect K is the transistor gain
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Sematech Results
Test process: Wafer Test Package Test Burn-In & Retest Characterize & Failure Analysis Data for devices failing some, but not all, tests. Scan-based Stuck-at pass pass 6 14 0 6 1 52 36 pass fail fail 1463 34 13 1251 pass fail 7 pass 1 pass 8 fail fail fail Scan-based delay
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IDDQ (5 mA limit)
pass fail pass fail
Functional
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Summary: IDDQ Test
IDDQ tests improve reliability, find defects
causing: Delay, bridging, weak faults Chips damaged by electro-static discharge No natural breakpoint for current threshold Get continuous distribution bimodal would be better Conclusion: now need stuck-fault, IDDQ, and delay fault testing combined Still uncertain whether IDDQ tests will remain useful as chip feature sizes shrink further
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References
M.L. Bushnell and V. D. Agrawal, Essentials
of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Boston:
Kluwer Academic Publishers, 2000, ISBN 0-7923-7991-8. For the material on a course taught by the authors at Rutgers University, and a complete bibliography from the above book, see website:
http://cm.bell-labs.com/cm/cs/who/va

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Fundamentals of Digital Test and DFT

Agrawal: Digital Test and DFT

Agrawal: Digital Test and DFT

VLSI Realization Process

Agrawal: Digital Test and DFT

Agrawal: Digital Test and DFT

Design for testability (DFT)

Chip area overhead and yield reduction Performance overhead

Agrawal: Digital Test and DFT

Cost of Manufacturing Testing in 2000AD

Present and Future*

Pin count Clock rate (MHz) Power (Watts)

100 - 900 200 - 730 1.2 - 61

160 - 1475 530 - 1100 2 - 96

* SIA Roadmap, IEEE Spectrum, July 1999

Agrawal: Digital Test and DFT

ADVANTEST Model T6682 ATE

Agrawal: Digital Test and DFT

LTX FUSION HF ATE

Agrawal: Digital Test and DFT

VLSI Chip Yield

Defect Level or Reject Ratio

Defect level (DL) is the ratio of faulty

Agrawal: Digital Test and DFT

Example: SEMATECH Chip

Defect level in ppm

Stuck-at fault coverage (%)

Agrawal: Digital Test and DFT

Agrawal: Digital Test and DFT

Why Model Faults?

Agrawal: Digital Test and DFT

Some Real Defects in Chips

Observed PCB Defects

Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985.

Common Fault Models

Agrawal: Digital Test and DFT

Single Stuck-at Fault

Three properties define a single stuck-at fault

Faulty circuit value Good circuit value

Test vector for h s-a-0 fault

sa0 sa1 sa0 sa1

sa0 sa1 20 Collapse ratio = ----- = 0.625 32

Agrawal: Digital Test and DFT

Summary: Fault Models

Agrawal: Digital Test and DFT

Problem and Motivation

Fault simulation Problem: Given

A circuit A sequence of test vectors A fault model

Agrawal: Digital Test and DFT

Fault simulator in a VLSI Design Process

Modeled Remove fault list tested faults Fault coverage ?

Test Delete compactor vectors

Fault Simulation Scenario

Circuit model: mixed-level

Signal states: logic

Agrawal: Digital Test and DFT

Fault Simulation Scenario (continued)

Agrawal: Digital Test and DFT

Essence of Fault Sim.

Agrawal: Digital Test and DFT

Agrawal: Digital Test and DFT

Random Sampling Model