Escolar Documentos
Profissional Documentos
Cultura Documentos
Andhra Pradesh
Name :G Sudhakar Reddy.
Designation :Senior Lecturer.
Branch :ECE
Institute :Government Polytechnic
Narsipatnam.
Year/Semester :III semester.
Subject :ELECTRONICS CIRCUITS-I.
Subject Code :EC-302.
Topic :FET& UJT.
DURATION :50 MIN
SUB TOPIC :Construction of
enhancement
MOSFET
TEACHING AIDS :Animation & photographs
EC302.35 to 36 1
OBJECTIVES
Upon the completion of this topic the student will be able to
know
EC302.35 to 36 2
RECAP
Mention
• MOSFET types
EC302.35 to 36 3
ENHANCEMENT MOSFET
EC302.35 to 36 4
Construction
• Holes are cut into this
Al layer SiO2 layer for making
source
contact with p+ source
Gate Drain
and drain regions.
Si o2 layer
------- • On the SiO2 layer, a
P+ +++ P+
metal (alluminium) layer is
overlaid covering the
Induced
P channel entire channel region from
source to drain.
N-type substrate
• This aluminum layer
constitutes the gate.
P channel Enhancement MOSFET
EC302.35 to 36 5
Construction • The area of MOSFET is
typically 5 square mills or
less.
Al layer • This area is extremely small
source Gate Drain being only about 5% of the
Si o2 layer area required for a bipolar
junction transistor.
------- • A parallel plate capacitor is
P+ +++ P+ formed with the metal areas
Induced of the gate and the
P channel semiconductor channel
acting as the electrodes of
N-type substrate the capacitor.
• The oxide layer acts as the
P channel Enhancement MOSFET dielectric between the
electrodes.
EC302.35 to 36 6
symbols
D
D
substrate
G G
S S
p channel enhancement MOSFET p channel
EC302.35 to 36 7
WORKING
Al layer • The substrate will be
source Gate Drain connected to the
Si o2 layer common terminal i.e.,
to the ground terminal.
-------
P+ +++ P+ • A negative potential will
Induced be applied to the gate.
P channel
EC302.35 to 36 8
WORKING
Al layer • This electric field originates
source from the induced positive
Gate Drain
charges on the semiconductor
Si o2 layer
side on the lower surface of
------- the SiO2 layer.
P+ +++ P+
Induced
P channel• The induced positive charge
become minority carriers in
N-type substrate the
n-type of substrate.
P channel Enhancement MOSFET
EC302.35 to 36 9
Enhancement MOSFET symbols
D
D
substrate
G
G
S S
N channel N channel
EC302.35 to 36 10
WORKING • It consists of a lightly doped
source Al layer p type substrate in to which
Gate
Drain two heavily Doped n type
Si o2 layer material are diffused.
++++
N+ ------ N+
• The surface is coated with
a layer of silicon dioxide(Sio2).
Induced
N channel
• Holes are cut through the
P-type substrate Sio2 to make contact with
n-type blocks.
EC302.35 to 36 11
WORKING
Al layer • Metal (Al) is deposited
source Gate
Drain through the Holes to form drain
++++ Si o2 layer
andsource terminals
N+ ------ N+
Induced
N channel • The surface area between
drain and source a metal plate
P-type substrate is deposited from which gate
terminal is taken out.
N channel Enhancement MOSFET
EC302.35 to 36 12
•Gate is insulated from the body of
Al layer
FET so it is called insulated gate
Gate FET(IGFET).
Drain
source
++++ Si o2 layer•Structurally there exits no channel
between source
N+ ------ N+ and drain so MOSFET some times
Induced called as N-channel enhancement
N channel type
EC302.35 to 36 13
WORKING OF THE ENHANCEMENT MOSFET
EC302.35 to 36 15
•Behaves as a capacitor with
gate metal acting as one
electrode, upper surface of the
substrate as other electrode and
Al layer
sio2 layer as dielectric medium.
Gate DrainSi o2
SOURCE
layer
+++
n+ --- n+ •When positive voltage is applied
Induced
n channel
to gate the capacitor begin to
charge.
p-type substrate
EC302.35 to 36 16
Al layer •Consequently positive
charges appears on the gate
Gate Drain
SOURCE
and negative charges appears
+++
in the substrate between
n+ --- n+
the drain and source.
Induced
n channel
•The n-channel thus formed is
p-type substrate called induced n-channel or
n-type inversion layer.
N channel Enhancement MOSFET •As VGS ,no.electrons in
the channel , ID .
EC302.35 to 36 17
• The minimum gate source voltage which produces the
induced n-channel is called threshold voltage VGS(th)
when VGS < VGS (th), ID=0.
EC302.35 to 36 18
• So the conductivity of the channel is enhanced
EC302.35 to 36 19
• Drain characteristics
•It is observed that the drain
Id(Ma) current has been enhanced on
application of negative gate
-10
V gs=-20 voltage.
-8 •This is the reason for calling it
-16
as enhancement MOSFET.
-6
-12
•By increasing the gate
-4
potential, pinch off voltage and
drain currents are increased.
-2
•The curves are similar to drain
0 -5 -10 -15 -20 characteristics of JFET.
Vds (v)
EC302.35 to 36 20
SUMMARY
we discussed that
• In enhancement MOSFETs there is absence of channel
between source &drain terminals.
EC302.35 to 36 21
QUIZ
EC302.35 to 36 22
QUIZ
EC302.35 to 36 23
• For enhancement only n-channel MOSFET, polarity of
VGS is
(A) negative
(B) positive
(C) zero.
(D) dependent the application of the device
EC302.35 to 36 24
Frequently Asked Questions
EC302.35 to 36 25
Frequently Asked Questions
EC302.35 to 36 26