DEPARTMENT OF TECHNICAL EDUCATION

ANDHRA PRADESH
Name : K.Sri Lakshmi
Designation : Lecturer in ECE
Institute : G.P.W. KAKINADA
scheme : C-05
Semester : III Semester
Branch : Computer Engineering
Sub Code & Title : CM-305, Digital Electronics
Topic : Logic families & flip-flops
Duration : 50 Minutes
Sub Topic : J K flip flop and edge & level triggering in flip
flops CM305.34 1

Teaching Aids : PPT

objectives

On completion of this period , the student would

be able to know

• Block diagram of J K flip- flop

• Working of J K flip –flop

• Truth table of J K flip-flop

• Concept of edge and level triggering in flip flops.

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 Recap
• RS Flip-flop
• D Flip-flop
• T Flip-flop

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 J-K flip flop

• The J-K flip flop is the most widely used flip flop.

• J K flip flop is also know as universal flip-flop because

J K flip flop can give the functionality of S R and T flip-
flop.

• J K flip- flop is used in construction of ripple counter,

decade synchronous counter.

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 Fig (1) shows a J – K flip flop Fig (2)is its logic symbol and the
inputs J and K are the data inputs CLK is the clock input and Q,
Q are the outputs.

J S Q J Q
Clock CLK
R Q CLK
K

K Q

Fig 1. J-K Flip Flop Fig 2 Logic Symbol

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Working of J-K Flip – flop

• When both the inputs J and K are ‘0’ the flip flop is in
hold state.

• In which the data inputs have no effect on output.

• When both the data inputs J and K are at logic 1

repeated clock pulses cause the outputs turn off, on, off
and so on called Toggle.

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• When J is high and K is low the J-K flip flop will set,

• when J=0 K=1 the flip flop will reset, as summarized in the
truth table.
Table 1. Truth table of JK flip flop

Inputs outputs
CLOCK comments
J K Q Q

HIGH 0 0 N.C N.C NO.Change

1 0 1 Reset
HIGH 0

1 0 Set
HIGH 1 0

HIGH 1 1 Qn+1
Toggle
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 Edge and Level Triggering

• Edge triggering : This means that the flip-flop is

changing the state either at the positive edge or negative
edge of the clock pulse.
• Output is sensitive to its inputs only at the transition of
the clock
• Level triggering: The flip-flop responds to the low and
high level of the clock signal.

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• The clock is thus a basic circuit controlling all the operations

•
These clock pulses initiate actions in flip flops and logic gates.

• A. simple square wave is called clock, which is shown below

fig(2).

Positive going or rising Edge

Negative going or Falling Edge

Fig 3 Clock Wave Forms

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Then according to the type of triggering these flip flops
are

1. Level triggered flip flops.

2. Edge Triggered flip flops.

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 S Q

CLK
R Q

level triggered flip flop

Fig 4. Level Triggered Flip Flops

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Edge triggering.

• The flip flop triggers at one instant of time i e, either at

+ ve edge.

• + ve edge is also known as leading edge

• - ve edge is also known as trailing edge.

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Positive edge triggered flip flop

J S
c
Q
c

CLK
R c
R Q
k

+ ve edge triggered Flip-flop

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• Edge triggered flip flop uses RC differentiation circuit to

convert a square wave pulse into spikes.

• Leading edge or rising edge is + ve spike.

• Trailing edge or negative edge is - ve spike.

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Negative edge triggered flip- flop.

J c
S Q
c
CLK o
R c
R Q
k

- ve edge triggered Flip-flop

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Summary

• J K Flip-Flop has two controlled inputs called J and K

• Output is fed back to the input in J K Flip Flop.

• The feed back causes J K Flip-Flop to toggle when

J=K=1

• This toggling feature is useful to make use of it in

construction of counter.

• J K Flip-Flop is also called universal flip-flop.

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Quiz

1. Which of the following flip-flop exhibits toggling

(a). S R

(b). D

(c) J K.

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1. Which of the following flop-flip are used in construction
of counter.

(a). S R

(b). JK

(c). D

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Frequently asked questions

1. Draw the logic diagram of J K Flip-flop and explain its

functioning of this with truth table.

3. Explain edge triggering and level triggering .

5. Explain the working of edge triggering with logic circuit

diagram.

7. List the application of J K Flip- flop.

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