X-MAP

A.SRINIVAS KIRAN(2011H140053G) R.SIRPI SRINIVASAN(2011H123031G) K.SANTOSH KUMAR(2011H140050G)

Outline
Introduction Process flow DAG extraction Minimization algorithm Packing into CLBs Conclusion

Introduction
Area optimization for implementing functions into FPGAs Xmap is an input-first greedy algorithm Developed by Kevin Karplus For Xilinx 3000 FPGAs

Xilinx 3000
It has 5-input 2 output CLBs Each CLB has two LUTs with a maximum of 4-inputs each and 5 distinct inputs combined

Process flow
Step 1: making the input function in SOP form into if-then-else-DAG Step 2: marking the nodes in the DAG Step 3: assigning the marked nodes to the CLBs

If-then-else DAG
Definition: the if-then-else operator is a ternary boolean function, with (if a then b else c) defined as ab+ac or (a+c)(a+b) Using this we can represent any boolean function Ex: ab = if a then b else FALSE a+b = if a then TRUE else b

If-then-else DAG
Steps to convert SOP to If-then-else DAG sorts the terms of T, grouping together those that dont use the first input variable (Td), those that use v1' (T0), and those that use v1 (T1) the expressions E1 and E0 consists of the product terms that use v1 and v1' respectively. The expression Ed consists of the product terms that neither use v1 nor v1'. If the expressions E1, E0 and Ed depend on more than one variable, they are recursively decomposed using the same procedure. builds the expression E as (if Ed then TRUE else (if VI then E1 else E0)).

Consider the example y = abc+abd+bd+aef+bcf The ordering of the terms b,a,c,d,f,e So b is the first input variable

aef

TRUE

b(ac+ad)+b(d+cf)

If(aef) then TRUE else(if b then (ac+ad) else (d+cf))

aef

TRUE b ac+ad d+cf

If b then (ac+ad) else d+cf

TRUE a ef b ac+ad d+cf

FALSE

If a then (ef) else FALSE

TRUE a e b ac+ad d+cf

FALSE

FALSE

If e then f else FALSE

TRUE a e b d+cf

FALSE

FALSE

If a then c else d

TRUE a e b

FALSE

FALSE

d d

TRUE

cf

If d then TRUE else cf

TRUE a e b

FALSE

FALSE

d d

TRUE c f FALSE

If c then f else FALSE

6 TRUE a e 1 FALSE

2
b

4
3 TRUE c f FALSE

FALSE

d d

Pseudo code for marking pass

Visit node 1 |signals(1)| =2 <= 5 so visit node 2 |signals(2)| =3 <= 5 so visit node 3 |signals(3)| =3 <= 5 so visit node 4 |signals(4)| =3 <= 5 so visit node 5 |signals(5)| =5 <= 5 so visit node 6 |signals(6)| =3 <= 5 so visit node y |Signals(y)| =6 > 5 so mark a descendent of y

Choose the descendant with highest signal set i.e. node 5 mark node 5 Now |signals(y)| = 4 <= 5 So mark y The marked nodes are node y and node 5

Packing into CLBs

Assigning to CLBs The algorithm takes a set of logic blocks L and two parameters: i, the maximum number of inputs for each function in a shared CLB, and t , the maximum total number of inputs in a shared CLB. First, all blocks with more than i inputs are removed from L as being unmergeable. The remaining set is sorted by the number of inputs to each block. The block with the most inputs is removed from L, and mergeability is checked with all remaining blocks, in decreasing order of number of inputs. If a legal merging is found, then the other block is also removed from L. The removal of blocks is continued until L is empty.

 Here i=4, since for this CLB block we can merge only those functions which have at most 4 inputs and total distinct number of inputs are 5 First node 5 has inputs as 5, so it is unmergeable. It is removed and put into a CLB. Next node is y which is put into second CLB

Conclusion
Xmap is 4.5 times faster than the chortle and generates 7% fewer blocks than it. Due to merging it also increases efficiency