2

8086 & Z80 P
Lec note 2
hsabaghianb @ kashanu.ac.ir
Microprocessors
2- 1
Outline
Microprocessors History Data width 8086 vs 8088 8086 pin description Z80 Pin description
Microprocessors
2- 2
Microprocessors
Microprocessors come in all kinds of varieties from the very simple to the very complex Depend on data bus and register and ALU width P could be 4-bit , 8-bit , 16-bit, 32-bit , 64-bit We will discuss two sample of it
Z80 as an 8-bit P and 8086/88 as an 16-bit P
All Ps have
Address bus Data bus Control Signals: RD, WR, CLK , RST, INT, . . .
Microprocessors
2- 3
History
Bus width
4 bit
4004 4040
8 bit
8008 8080 8085 Z80
16 bit
8088/6 80186 80286 Z8000 Z8001 Z8002 68006 68008 68010
Microprocessors
32 bit
80386 80486
64 bit
80860 pentium
Company intel
zilog
Motorola
6800 6802 6809
68020 68030 68040

2- 4
Internal and External Bus

Internal bus is a pathway for data transfer between registers and ALU in the Ps External bus is available externally to connect to RAM, ROM and I/O Int. and Ext. Bus width may be different For example
In 8088 Int. Bus is 16-bit , Ext. bus is 8-bit In 8086 Int. Bus is 16-bit , Ext. bus is 16-bit
Microprocessors
2- 5
8086 vs 8088
Only external bus of 8088 is 8_bit
U? 3 3 22 1 9 21 1 8 MN REA DY CL K RES ET IN T R 1 A D0 1 AD1 1 A D2 1 AD3 1 A D4 1 AD5 1 A D6 9 A D7 8 A D8 7 A D9 6 A D 1 05 A D 1 14 A D 1 23 A D 1 32 A D 1 43 A D 1 53 A 1 6 / S 33 A 1 7 /S 4 3 A 1 8 / S 53 A 1 9 /S 6 6 5 4 3 2 1 0 3 3 22 1 9 21 1 8 U? MN REA DY CL K RES ET IN T R 1 A D0 1 AD1 1 A D2 1 AD3 1 A D4 1 AD5 1 A D6 9 A D7 8 A8 7 A9 6 A 1 0 5 A1 1 4 A 1 2 3 A1 3 2 A 1 4 3 A1 5 3 A 1 6 / S 33 A 1 7 /S 4 3 A 1 8 / S 53 A 1 9 /S 6 SSO 6 5 4 3 2 1 0
8_bit Data Bus 20_bit Address
16_bit Data Bus 20_bit Address

9 8 7 6 5
9 8 7 6 5
3 4 B H E /S 7 26 D E N 27 D T /R 2 8 M /IO 3 2 R D 29 W R 25 A L E 24 IN T A
3 4
3 0 3 1 1 7 23
HL DA HOL D NMI TE S T 8 0 8 6 M IN
3 0 3 1 1 7 23
HL DA HOL D NMI TE S T 8 0 8 8 M IN
26 D E N 27 D T /R 2 8 IO /M 3 2 R D 29 W R 25 A L E 24 IN T A
8086
8088
2- 6
Microprocessors
8086 Pin Assignment
Microprocessors
2- 7
8086 Pin Description

Vcc (pin 40) : Power Gnd (pin 1 and 20) : Ground AD0..AD7 , A8..A15 , A19/S6, A18/S5, A17/S4, A16/S3 : 20 -bit Address Bus MN/MX (input) : Indicates Operating mode READY (input , Active High) : take P to wait state CLK (input) : Provides basic timing for the processor RESET (input, Active High) : At least 4 clock cycles Causes the P immediately terminate its present activity. TEST (input , Active Low) : Connect this to HIGH HOLD (input , Active High) : Connect this to LOW (BR) HLDA (output , Active High) : Hold Ack (BG) INTR (input , Active High) : Interrupt request INTA (output , Active Low) : Interrupt Acknowledge NMI (input , Active High) : Non-maskable interrupt
hsabaghianb @ kashanu.ac.ir Microprocessors
2- 8
8086 Pin Description

DEN (output) : Data Enable. It is LOW when processor wants to
receive data or processor is giving out data (to74245)

DT/R (output) : Data Transmit/Receive. When High, data from P to memory When Low, data is from memory to P (to74245 dir) IO/M (output) : If High P access I/O Device.
If Low P access memory RD (output) : When Low, P is performing a read operation WR (output) : When Low, P is performing a write operation ALE (output) : Address Latch Enable , Active High Provided by P to latch address When HIGH, P is using AD0..AD7, A19/S6, A18/S5, A17/S4, A16/S3 as address lines
2- 9
Z80 CPU Pin Assignment

M1 27 19 20 21 22 28 18 24 16 17 26 25 23 14 15 12 8 7 9 10 13 30 31 32 33 34 35 36 37 38 39
System Control Lines
M REQ IO RQ RD WR R FSH HA LT -
C PU Control Lines
W AIT IN T NMI RESET -
Z - 80 CPU
40 1 2 3 4 5
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 D4 D5 D6 D7
Address Bus
Bus Control Lines
B U SR Q B USAK + 5V GND
Data Bus
6 11 29
Microprocessors
2-
Z80 Pin Description

A15-A0 :
Address bus (output, active high, 3-state). Used for accessing the memory and I/O ports During the refresh cycle the I is put on this bus.
D7-D0 :
Data Bus (input/output, active high, 3-state). Used for data exchanges with memory, I/O and interrupts.
RD:
Read (output, active Low, 3-state) indicates that the CPU wants to read data from memory or I/O
WR:
Write (output, active Low, 3-state) indicates that the CPU data bus holds valid data to be stored at the addressed memory or I/O location.
2-
Z80 Pin Description

MREQ IORQ M1
Memory Request (output, active Low, 3-state). Indicates memory read/write operation. See M1 Input/Output Request(output,active Low,3-state) Indicates I/O read/write operation. See M1 Machine Cycle One (output, active Low). Together with MREQ indicates opcode fetch cycle Together with IORQ indicates an Int Ack cycle
RFSH
Refresh (output, active Low). Together with MREQ indicates refresh cycle. Lower 7-bits address is refresh address to DRAM
Microprocessors
2-
Z80 Pin Description

INT Interrupt Request (input, active Low). generated by I/O devices. Checked at the end of current instruction If flip-flop (IFF) is enabled. NMI Non-Maskable Interrupt (Input, negative edge-triggered). Checked at the end of current Instruction Higher priority than INT. Independent from IFF Status Forces CPU restart at 0066H.
Microprocessors
2-
Z80 Pin Description

BUSREQ Bus Request (input, active Low). higher priority than NMI recognized at the end of current machine cycle forces the CPU address bus, data bus, and MREQ, IORQ, RD, and WR to high-imp. BUSACK Bus Acknowledge (output, active Low) indicates to the requesting device that address, data, and control signals have entered their high-impedance states.
2-
Z80 Pin Description

RESET Reset (input, active Low). Must be active for three clock cycles Initializes the CPU as follows: Resets the IFF Clears the PC and I and R Sets the interrupt to Mode 0 During reset time: address and data go high-impedance all control (out) signals go inactive state
Microprocessors
2-
Z80 CPU
8
IN T E R N A L D A T A B U S (8 B IT )
B U F F E R F F'
MUX
IN S T R U C T IO N R E G IS T E R
W' Z' W
MUX A
Z
DATA BUS
TMP A'
B' D' H'
C' E' L' IX IY SP
B D H
C E L
ACT
DECODER
CO N TRO LLE R SEQUENCER
A LU
PC k k 16
IN T E R N A L A D D R E S S B U S (16 B IT )
CONTROL S E C T IO N
B U F F E R
ADDRESS BUS
13
IN T E R N A L C O N T R O L B U S
B U F F E R
C O N TR O L B U S
Microprocessors
2-
Z80 Programming Model
Microprocessors
2-
Register Set
A : Accumulator Register F : Flag register Two sets of six general-purpose registers
may be used as 8-bit A F B C D E H L (A F B C D E H L)
or in pairs as 16-bit AF BC DE HL (AF BC DE HL)
The Alternative registers (A F B C D E H L) not visible to the programmer but can access via:
EXX EX AF, AF (BC)<->(BC') , (DE)<->(DE') , (HL)<->(HL') (AF)<->(AF')
what is this instruction useful for?

2-
Register Set(cont)
4 (16-bit) registers hold memory address (pointers)
index registers (IX) and (IY) are 16-bit memory pointers 16 bit stack pointer (SP) Program counter (PC)
Program counter (PC)

PC points to the next opcode to be fetched from ROM when the P places an address on the address bus to fetch the byte from memory, it then increments the program counter by one to the next location
Special purpose registers

I : Interrupt vector register. R : memory Refresh register
Microprocessors
2-
Flag Register
7 6 5 4 3 2 1 0
S Z X H X
S Sign Flag (1:negativ)* Z Zero Flag (1:Zero)
P V
N C
H Half Carry Flag (1: Carry from Bit 3 to Bit 4)** P Parity Flag (1: Even) V Overflow Flag (1:Overflow)* N Operation Flag (1:previous Operation was subtraction)** C Carry Flag (1: Carry from Bit n-1 to Bit n, with n length of operand) *: 2-complement number representation **: used in DAA-operation for BCD-arithmetic
2-
DAA - Decimal Adjust Accumulator

Adjusts the content of the Accumulator A for BCD addition and subtraction operations such as ADD, ADC, SUB, SBC, and NEG according to the table:
before DAA Op ADD ADC N 0 0 0 0 0 0 0 0 0 1 1 1 1 C 0 0 0 0 0 0 1 1 1 0 0 1 1 Bits 4-7 0-9 0-8 0-9 A-F 9-F A-F 0-2 0-2 0-3 0-9 0-8 7-F 6-F H 0 0 1 0 0 1 0 0 1 0 1 0 1 Bits 0-3 0-9 A-F 0-3 0-9 A-F 0-3 0-9 A-F 0-3 0-9 6-F 0-9 6-F after DAA A=A+.. 00 06 06 60 66 66 60 66 66 00 FA A0 9A C 0 0 0 1 1 1 1 1 1 0 0 1 1 2-
SUB SBC NEG
Microprocessors
Instruction cycles, machine cycles and T-states

Instruction cycle is the time taken to complete the execution of an instruction Machine cycle is defined as the time required to complete one operation of accessing memory, accessing IO, etc. T-state = 1/f (f:Z80 Clock Frequency) f= 4MHZ T-state=0.25 uS
Microprocessors
2-
Basic CPU Timing Example
Microprocessors
2-
Opcode Fetch Bus Timings (M1 Cycle)
Microprocessors
2-
The R register
Is increased at every first machine cycle (M1). Bit 7 of it is never changed by this; only the lower 7 bits are included in the addition. So bit 7 stays the same Bit 7 can be changed using the LD R,A instruction. LD A,R a nd LD R,A access the R register after it is increased R is often used in programs for a random value, which is good but of course not truly random. the block instructions decrease the PC with two, so the instructions are re-executed.
2-
Memory read/write cycle
Microprocessors
2-
Adding One Wait State to an M1 Cycle
Microprocessors
2-
Adding One Wait State to Any Memory Cycle
Microprocessors
2-
IO read/write cycle
During I/O operations a single wait state is automatically inserted

2-
Bus Request/Acknowledge Cycle
Microprocessors
2-
Interrupt Request/Acknowledge Cycle
Two wait states are automatically added to this cycle

2-
Non-Maskable Interrupt Request Operation
Microprocessors
2-
M1 Refresh Cycle
Takes 4T to 6Ts Z80 includes built in circuitry for refreshing DRAM This simplifies the external interfacing hardware DRAM consists of MOS transistors, which store Information as capacitive charges; each cell needs to be periodically refreshed During T3 and T4 (when Z80 is performing internal ops), the low order address is used to supply a 7-bit address for refresh
2-
Wait Signal
the Z80 samples the wait signal during T2 if low then Z80 adds wait states to extend the machine cycle used to interface memories with slow response time Slow memory is low cost
Microprocessors
2-
Interrupts
There are two types of interrupts: non mask-able (NMI)
Could not be masked Jump to 0066H of memory
mask-able(INT)
Has 3 mode Can be set with the IM x Instruction IM 0 sets Interrupt mode 0 IM 1 sets Interrupt mode 1 IM 2 sets Interrupt mode 2
2-
Interrupt Modes
Mode 0:
An 8 bit opcode is Fetched from Data BUS and executed The source interrupt device must put 8 bit opcode at data bus 8 bit opcode usually is RST p instructions
Mode 1:
A jump is made to address 0038h No value is required at data bus
Mode 2:
A jump is made to address (register I 256 + value from interrupting device that puts at bus) I is high 8 bit of interrupt vector Value is low 8 bit of interrupt vector
2-
Microprocessors
2-
Z80 CPU Instruction Description

158 different instruction types Including all 78 of the 8080A CPU. Instruction groups
Load and Exchange Block Transfer and Search Arithmetic and Logical Rotate and Shift Bit Manipulation (Set, Reset, Test) Jump, Call, and Return Input/Output Basic CPU Control
Microprocessors
2-
Addressing Modes
Immediate Immediate Extended Modified Page Zero Addressing (rst p) Relative Addressing
Jump Relative (2 byte) One Byte Op Code 8-Bit Twos Complement Displacement (A+2)
Extended Addressing
Absolute jump One byte opcode 2 byte address
Indexed Addressing
(Index Register + Displacement) (IX+d) 2 byte opcode 1 byte displacement
2-
Addressing Modes(cont.)
Register Addressing
LD C,B
Implied Addressing
Op Code implies other operand(s) ADD E
Register Indirect Addressing

16-bit CPU register pair as pointer (such as HL) ADD (HL)
Bit Addressing
set, reset, and test instructions. SET 3,A RES 7,B
2-

2

Enviado por

Dados do documento

Descrição original:

Direitos autorais

Formatos disponíveis

Compartilhar este documento

Compartilhar ou incorporar documento

Opções de compartilhamento

Você considera este documento útil?

Este conteúdo é inapropriado?

Direitos autorais:

Formatos disponíveis

2

Enviado por

Direitos autorais:

Formatos disponíveis

8086 & Z80 P

6800 6802 6809

68020 68030 68040

Internal and External Bus

8_bit Data Bus 20_bit Address

16_bit Data Bus 20_bit Address

8086 Pin Assignment

8086 Pin Description

8086 Pin Description

receive data or processor is giving out data (to74245)

Z80 CPU Pin Assignment

System Control Lines

W AIT IN T NMI RESET -

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 D4 D5 D6 D7

Bus Control Lines

Z80 Pin Description

Z80 Pin Description

Z80 Pin Description

Z80 Pin Description

Z80 Pin Description

B' D' H'

C' E' L' IX IY SP

CO N TRO LLE R SEQUENCER

Z80 Programming Model

or in pairs as 16-bit AF BC DE HL (AF BC DE HL)

what is this instruction useful for?

Program counter (PC)

Special purpose registers

DAA - Decimal Adjust Accumulator

SUB SBC NEG

Instruction cycles, machine cycles and T-states

Basic CPU Timing Example

Opcode Fetch Bus Timings (M1 Cycle)

Memory read/write cycle

Adding One Wait State to an M1 Cycle

Adding One Wait State to Any Memory Cycle

During I/O operations a single wait state is automatically inserted

Bus Request/Acknowledge Cycle

Interrupt Request/Acknowledge Cycle

Two wait states are automatically added to this cycle

Non-Maskable Interrupt Request Operation

Z80 CPU Instruction Description

Register Indirect Addressing

Você também pode gostar